SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC

This paper proposes a SAT-based formulation to evaluate the logical capacity of VIA-configurable block templates. The proposed solution is able to support any user-defined regular layout. The proposed SAT formulation was sucessufully applied to the three main VCSA fabrics in the literature considering transistor networks from an open cell library and transistor networks representing all 4-input Boolean functions. We observed that the number of literals and variables in the SAT formulation grows nearly quadratically with respect to the number of transistors in the VCSA fabric. We also noticed that the average runtime of the SAT solver presents a strong dependence on the input VCSA fabric.

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