From algebraic semantics to denotational semantics for Verilog

This paper considers how the algebraic semantics for Verilog relates with its denotational semantics. Our approach is to derive the denotational semantics from the algebraic semantics. We first present the algebraic laws for Verilog. Every program can be expressed as a guarded choice that can model the execution of a program. In order to investigate the parallel expansion laws, a sequence is introduced, which indicates the instantaneous action is due to which exact parallel component. A normal form is defined for each program by using the locality sequence. We provide a strategy for deriving the denotational semantics based on the algebraic normal form. Using the strategy, the denotational semantics for every program can be calculated. Program equivalence can also be explored by using the derived denotational semantics.

[1]  He Jifeng,et al.  From CSP to hybrid systems , 1994 .

[2]  Jonathan P. Bowen Combining Operational Semantics, Logic Programming and Literate Programming in the Specification and Animation of the Verilog Hardware Description Language , 2000, IFM.

[3]  He Jifeng,et al.  Integrating variants of DC , 2004 .

[4]  Zohar Manna,et al.  Verification of concurrent programs, Part I: The temporal framework , 1981 .

[5]  Gordon G. Pace,et al.  Hardware design based on Verilog HDL , 1998 .

[6]  Jifeng He,et al.  An Operational Semantics of a Simulator Algorithm , 2000, PDPTA.

[7]  Gordon J. Pace,et al.  Formal reasoning with Verilog HDL , 1998 .

[8]  Jordan Dimitrov Operational semantics for Verilog , 2001, Proceedings Eighth Asia-Pacific Software Engineering Conference.

[9]  Michael J. C. Gordon,et al.  Relating Event and Trace Semantics of Hardware Description Languages , 2002, Comput. J..

[10]  Jifeng He,et al.  An Approach to the Specification and Verification of a Hardware Compilation Scheme , 2001, The Journal of Supercomputing.

[11]  He Jifeng,et al.  An algebraic approach to hardware/software partitioning , 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

[12]  Zohar Manna,et al.  The Temporal Logic of Reactive and Concurrent Systems , 1991, Springer New York.

[13]  Nimal Nissanke Realtime systems , 1997, Prentice Hall series in computer science.

[14]  Augusto Sampaio,et al.  Normal form approach to compiler design , 1993, Acta Informatica.

[15]  Gerardo Schneider,et al.  Towards a Formal Semantics of Verilog Using Duration Calculus , 1998, FTRTFT.

[16]  Jifeng He,et al.  Soundness, Completeness and Non-redundancy of Operational Semantics for Verilog Based on Denotational Semantics , 2002, ICFEM.

[17]  He Jifeng,et al.  Formalising VERILOG , 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

[18]  C. A. R. Hoare,et al.  Laws of programming , 1987, CACM.

[19]  Shengchao Qin,et al.  Hardware/Software Partitioning in Verilog , 2002, ICFEM.

[20]  Ben C. Moszkowski,et al.  Executing temporal logic programs , 1986, Seminar on Concurrency.

[21]  Jifeng He,et al.  Deriving operational semantics from denotational semantics for Verilog , 2001, Proceedings Eighth Asia-Pacific Software Engineering Conference.

[22]  Michael R. Hansen,et al.  Chopping a point , 1996 .

[23]  Zohar Manna,et al.  Temporal Verification of Reactive Systems , 1995, Springer New York.

[24]  Michael R. Hansen,et al.  Duration calculus: Logical foundations , 1997, Formal Aspects of Computing.

[25]  Zohar Manna,et al.  Temporal verification of reactive systems - safety , 1995 .

[26]  Augusto Sampaio An Algebraic Approach to Compiler Design , 1993, AMAST Series in Computing.

[27]  Shengchao Qin,et al.  From Statecharts to Verilog: a formal approach to hardware/software co-specification , 2006, Innovations in Systems and Software Engineering.

[28]  Shengchao Qin,et al.  Constructing hardware/software interface using protocol converters , 2001, Proceedings Second Asia-Pacific Conference on Quality Software.

[29]  Jifeng He,et al.  From Operational Semantics to Denotational Semantics for Verilog , 2001, CHARME.

[30]  Ieee Standards Board IEEE Standard hardware Description language : based on the Verilog hardware description language , 1996 .

[31]  Gordon J. Pace,et al.  The Semantics of Verilog Using Transition System Combinators , 2000, FMCAD.

[32]  Gordon J. Pace,et al.  Simulation Approach to Provably Correct Hardware Compilation , 1994, FTRTFT.

[33]  Michael J. C. Gordon,et al.  The semantic challenge of Verilog HDL , 1995, Proceedings of Tenth Annual IEEE Symposium on Logic in Computer Science.

[34]  C. A. R. Hoare,et al.  A Calculus of Durations , 1991, Inf. Process. Lett..