论文信息 - High Defect Coverage with Low-Power Test Sequences in a BIST Environment

High Defect Coverage with Low-Power Test Sequences in a BIST Environment

A new technique, random single-input change (RSIC) test generation, generates low-power test patterns that provide a high level of defect coverage during low-power BIST of digital circuits. The authors propose a parallel BIST implementation of the RSIC generator and analyze its area-overhead impact.

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