PLL at 2.4 GHz with reduced reference spurs

This paper presents a frequency synthesizer for the frequency of 2.4 GHz, which were designed to present a reduced level of reference frequency spurs. Parts of the synthesizer were fabricated in a standard 0.18 μm CMOS process, whose architecture is based on a Phase-Locked Loop (PLL) with an integer divider in the feedback loop and was designed to work with a voltage supply of only 1.8 V. Some building blocks are reused thus the novelty of this paper is presenting a PLL with two new blocks for reducing the magnitude of spurs of the process, e.g., a sample-and-hold circuit and a quantizer circuit (with N quantizing levels). The PLL behaviour was simulated for a few number of levels — N={32, 64, 128} — and for a variety of loop-filters. As showed by the simulations, the quantizations provide an additional reduction of the reference-frequency spurs into the output of the PLL. Moreover, the locking time is kept low even after including the two new circuit blocks in the loop