Automatic instruction set extension and utilization for embedded processors

There is a growing demand for application-specific embedded processors in system-on-a-chip designs. Current tools and design methodologies often require designers to manually specialize the processor based on an application. Moreover, the use of the new complex instructions added to the processor is often left to designers' ingenuity. We present a solution that automatically groups dataflow operations in the application software as potential new complex instructions. The set of possible instructions is then automatically used for code generation combined with high-level arithmetic optimizations using symbolic algebra. Symbolic arithmetic manipulations provide a novel and effective method for instruction selection that is necessary due to the complexity of the automatically identified instructions. We have used our methodology to automatically add new instructions to Tensilica processors for a set of examples. Our results show that our tools improve designers productivity and efficiently specialize an embedded processor for the given application such that the execution time is greatly improved.

[1]  Jan Hoogerbrugge,et al.  ConCISe: a compiler-driven CPLD-based instruction set accelerator , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

[2]  Fabien Coelho,et al.  Using algebraic transformations to optimize expression evaluation in scientific code , 1998, Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192).

[3]  Cesare Alippi,et al.  A DAG-Based Design Approach for Reconfigurable VLIW Processors , 1999, DATE.

[4]  David A. Cox,et al.  Ideals, Varieties, and Algorithms , 1997 .

[5]  Andreas Moshovos,et al.  CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit , 2000, ISCA '00.

[6]  임종인,et al.  Gröbner Bases와 응용 , 1995 .

[7]  Henk Corporaal,et al.  Designing domain-specific processors , 2001, CODES '01.

[8]  Albert Wang,et al.  Hardware/software instruction set configurability for system-on-chip processors , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[9]  Steven S. Muchnick,et al.  Advanced Compiler Design and Implementation , 1997 .

[10]  Giovanni De Micheli,et al.  Polynomial circuit models for component matching in high-level synthesis , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[11]  Majid Sarrafzadeh,et al.  Instruction generation for hybrid reconfigurable systems , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[12]  Paolo Ienne,et al.  Automatic application-specific instruction-set extensions under microarchitectural constraints , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[13]  Dr. Rainer Leupers Code Optimization Techniques for Embedded Processors , 2000, Springer US.