22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process

Energy efficiency in mobile devices is a pivotal criteria from the overall system point of view, Although the 7,5Gb/s 8Gb LPDDR5 [1], with low-power schemes (internal data copy, dynamic-voltage-frequency scaling (DVFS), and a deep-sleep mode (DSM)), achieves improved energy efficiency compared to the previous LPDDR4X [2], the market demands for higher density and speed gradually increase for high-end applications including hand-held artificial intelligence (AI) and advanced driver assistance system (ADAS), To achieve higher density and speed in a power-efficient manner, this paper proposes a 8,5Gb/s 12Gb LPDDR5 with a hybrid bank architecture (split/merged bank), a skew-tolerant scheme, bus-based ROBI AC, and speed-boosting techniques based on 2nd generation 10nm DRAM process, Adopting a hybrid bank architecture and skew-tolerant scheme enables high speed and power-optimization for each bank-mode in high density memories, Moreover, bus-based RDBI AC achieves 2,1 % current gain and command-based WCK control scheme achieves 36mA saving at WCK-always-on mode, The speed-boosting techniques (duty-cycle correction (DCC), an active-resonant load, and at-tap DFE receiver) provide improved operating speeds from 7,5Gb/s to 8,5Gb/s@VDD2H = 1, 05V, where the read/write DQ valid windows are 0,60UI and 0.64UI (1UI = 118ps).