Bus-invert coding for low-power I/O - a decomposition approach

This paper proposes a new bus-invert coding scheme for reducing the number of bus transitions. Unlike the previous schemes in which the entire bus lines or one subset of the bus fines are considered for bus-invert coding, in the proposed scheme the bus lines are partitioned and each partitioned group is considered independently for bus-invert coding to maximize the effectiveness of reducing the total number of bus transitions. Experimental results show that the decomposed bus-invert coding scheme reduces the total number of bus transitions by 47.2% and 11.9% on average than those of the conventional and the partial bus-invert coding schemes, respectively.

[1]  Kiyoung Choi,et al.  Reduction of bus transitions with partial bus-invert coding , 1998 .

[2]  Nikil D. Dutt,et al.  1995 high level synthesis design repository , 1995 .

[3]  Luca Benini,et al.  Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems , 1997, Proceedings Great Lakes Symposium on VLSI.

[4]  Chi-Ying Tsui,et al.  Saving power in the control path of embedded processors , 1994, IEEE Design & Test of Computers.

[5]  Dake Liu,et al.  Power consumption estimation in CMOS VLSI chips , 1994, IEEE J. Solid State Circuits.

[6]  Mircea R. Stan,et al.  Bus-invert coding for low-power I/O , 1995, IEEE Trans. Very Large Scale Integr. Syst..