A Low Power Sample-and-Hold Circuit for Pipelined A/D Converter

A low power sample-and-hold circuit for a 10-bit 20 MS/s pipelined A/D converter has been designed,which is implemented in a 0.6 μm double-poly double-metal CMOS process.The S/H circuit is realized in switched-capacitor topology.Differential signal input topology is used to make the circuit less sensitive to interference.A common-mode feedback circuit is also used to stabilize the common-mode output to a desired level,thus improving the precision of the S/H.Furthermore,the S/H circuit consumes only 5 mW power at 5 V supply voltage with a low power operational transconductance amplifier(OTA).The A/D converter based on this S/H circuit achieves a SNDR of 58 dB at 20 MHz sampling rate,and the power dissipation is only 49 mW.