SAT Based Fitness Scoring for Digital Circuit Evolution

Evolutionary computation uses Darwinian principles to find solutions from a given search space and forms the basis for evolving digital circuits. One of the most computationally expensive steps in evolutionary computation is the comparison of the candidate circuit or chromosome with the target truth table. We propose to use a satisfiability solver, to improve upon the efficiency of this process, which is traditionally done using exhaustive simulation. The paper presents an implementation of the satisfiability solver, which is in turn used to develop a digital circuit evolution methodology based on the principles of cartesian genetic programming. The proposed methodology performs better, in terms of speed of design space exploration, for circuits whose behavior can be expressed compactly in terms of conjunctive normal form clauses. For illustration purposes, the proposed methodology has been used to evolve various commonly used digital circuits and a few benchmarks.

[1]  Lukás Sekanina,et al.  This is an author-created accepted version of the paper: Vasicek Z., Sekanina L.: Formal Verification of Candidate Solutions for Post- Synthesis Evolutionary Optimization in Evolvable Hardware. Genetic Programming and Evolvable Machines, Spec. Issue on Evolvable Hardware , 2011 .

[2]  Lukás Sekanina,et al.  Evolvable Hardware , 2009, Handbook of Natural Computing.

[3]  Moritoshi Yasunaga,et al.  An Online EHW Pattern Recognition System Applied to Face Image Recognition , 2009, EvoWorkshops.

[4]  Julian Francis Miller,et al.  Cartesian genetic programming , 2000, GECCO '10.

[5]  Marc Thurley,et al.  sharpSAT - Counting Models with Advanced Component Caching and Implicit BCP , 2006, SAT.

[6]  Leandro Maia Silva,et al.  Improving SAT-based Combinational Equivalence Checking through circuit preprocessing , 2008, 2008 IEEE International Conference on Computer Design.

[7]  Kalyanmoy Deb,et al.  A Comparative Analysis of Selection Schemes Used in Genetic Algorithms , 1990, FOGA.

[8]  A. P. Shanthi,et al.  Practical and scalable evolution of digital circuits , 2009, Appl. Soft Comput..

[9]  Carlos A. Coello Coello,et al.  Extracting and re-using design patterns from genetic algorithms using case-based reasoning , 2003 .

[10]  Lukás Sekanina,et al.  How to evolve complex combinational circuits from scratch? , 2014, 2014 IEEE International Conference on Evolvable Systems.

[11]  G. S. Tseitin On the Complexity of Derivation in Propositional Calculus , 1983 .

[12]  Stephanie Kemper SAT-based Verification for Timed Component Connectors , 2009, Electron. Notes Theor. Comput. Sci..

[13]  Julian F. Miller,et al.  Designing Electronic Circuits Using Evolutionary Algorithms. Arithmetic Circuits: A Case Study , 2007 .

[14]  Lukás Sekanina,et al.  When does Cartesian genetic programming minimize the phenotype size implicitly? , 2010, GECCO '10.

[15]  Julian Francis Miller,et al.  Principles in the Evolutionary Design of Digital Circuits—Part II , 2000, Genetic Programming and Evolvable Machines.

[16]  Lukás Sekanina,et al.  Evolutionary Design of Digital Circuits: Where Are Current Limits? , 2006, First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06).

[17]  Jason Cong,et al.  Optimality Study of Logic Synthesis for LUT-Based FPGAs , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Christoph Scholl,et al.  Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets , 2007, 2007 Asia and South Pacific Design Automation Conference.

[19]  Julian Francis Miller,et al.  Self-modifying cartesian genetic programming , 2007, GECCO '07.

[20]  Jim Tørresen,et al.  A Scalable Approach to Evolvable Hardware , 2002, Genetic Programming and Evolvable Machines.

[22]  Alexander Sudnitson,et al.  Using SAT-Based Techniques in Low Power State Assignment , 2011, J. Circuits Syst. Comput..

[23]  Tughrul Arslan,et al.  Evolvable Components—From Theory to Hardware Implementations , 2005, Genetic Programming and Evolvable Machines.

[24]  M. Sipper,et al.  Toward robust integrated circuits: The embryonics approach , 2000, Proceedings of the IEEE.

[25]  John R. Koza,et al.  Genetic Programming IV: Routine Human-Competitive Machine Intelligence , 2003 .

[26]  Julian Francis Miller,et al.  Redundancy and computational efficiency in Cartesian genetic programming , 2006, IEEE Transactions on Evolutionary Computation.

[27]  Julian Francis Miller,et al.  The Automatic Acquisition, Evolution and Reuse of Modules in Cartesian Genetic Programming , 2008, IEEE Transactions on Evolutionary Computation.

[28]  Marco Platzner,et al.  Advanced techniques for the creation and propagation of modules in cartesian genetic programming , 2008, GECCO '08.

[29]  Axel W. Krings,et al.  The test vector problem and limitations to evolving digital circuits , 2000, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware.

[30]  Peter J. Bentley,et al.  Towards development in evolvable hardware , 2002, Proceedings 2002 NASA/DoD Conference on Evolvable Hardware.

[31]  E. Stomeo,et al.  Generalized Disjunction Decomposition for Evolvable Hardware , 2006, IEEE Transactions on Systems, Man, and Cybernetics, Part B (Cybernetics).