Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems

This paper characterizes the potentially catastrophic effect of crosstalk glitches on representative circuit implementations of two widely used asynchronous protocols. It is demonstrated that the crosstalk glitches can induce false events, which can undesirably propagate into asynchronous interface circuits and may cause system failure. Conventionally, to a circuit designer, glitch propagation (GP) due to aggressor-to-quiet-line crosstalk (AQX) in asynchronous handshake schemes can only be observed through circuit-level analysis/simulation. In this paper, circuit-level analysis is first performed to prove that even optimized conventional asynchronous circuits allow crosstalk glitches produced over moderate-length interconnects (1.5 mm) to propagate. This is a precursor to a more problematic crosstalk glitch occurrence due to further scaling of technologies. To warn the digital designers from GP due to AQX, a novel modeling technique is proposed. This modeling method works at the logic level to facilitate asserting asynchronous interface robustness to crosstalk glitches. This model can accurately identify the possibility of intrinsic (to the asynchronous interface) crosstalk GP in asynchronous circuits at the logic level and, hence, provides a foundation to formally verify such circuits. To our knowledge, this is the first work on modeling GP due to AQX at the logic level for asynchronous circuits.

[1]  J. Paul Roth,et al.  Diagnosis of automata failures: a calculus and a method , 1966 .

[2]  Jeong-Gun Lee,et al.  Differential Value Encoding for Delay Insensitive Handshake Protocol , 2005, IEICE Trans. Inf. Syst..

[3]  Kenneth Y. Yun,et al.  Automatic synthesis of extended burst-mode circuits. II. (Automaticsynthesis) , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Anurag Mittal,et al.  Nano-CMOS Circuit and Physical Design , 2004 .

[5]  Daniel Marcos Chapiro,et al.  Globally-asynchronous locally-synchronous systems , 1985 .

[6]  Rajendran Panda,et al.  Analysis of noise avoidance techniques in DSM interconnects using a complete crosstalk noise model , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[7]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[8]  H. Pedram,et al.  FPGA Implementation of Gated Clock based Globally Asynchronous Locally Synchronous Wrapper Circuits , 2007, 2007 International Symposium on Signals, Circuits and Systems.

[9]  William John Bainbridge,et al.  Delay insensitive system-on-chip interconnect using 1-of-4 data encoding , 2001, Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001.

[10]  Simon W. Moore,et al.  Demystifying Data-Driven and Pausible Clocking Schemes , 2007, 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07).

[11]  Sanjeev K. Jain,et al.  Active noise cancellation using aggressor-aware clamping circuit for robust on-chip communication , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[12]  Dhanistha Panyasak,et al.  Circuits , 1995, Annals of the New York Academy of Sciences.

[13]  Kevin Barraclough,et al.  I and i , 2001, BMJ : British Medical Journal.

[14]  Bo Fu,et al.  On Hamming Product Codes With Type-II Hybrid ARQ for On-Chip Interconnects , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[15]  Kenneth S. Stevens,et al.  The Family of 4-phase Latch Protocols , 2008, 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems.

[16]  Alexandre Yakovlev,et al.  Phase-Encoding for On-Chip Signalling , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[18]  Stephen B. Furber,et al.  Chain: A Delay-Insensitive Chip Area Interconnect , 2002, IEEE Micro.

[19]  Rung-Bin Lin,et al.  Inter-Wire Coupling Reduction Analysis of Bus-Invert Coding , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[20]  Steve Furber,et al.  Principles of Asynchronous Circuit Design: A Systems Perspective , 2010 .

[21]  R. Negulescu,et al.  1.1-GDI/s transmission between pausible clock domains , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[22]  D. Dill,et al.  Automatic Synthesis of Extended Burst-Mode Circuits : Part II ( Automatic Synthesis ) , 1996 .

[23]  Kenneth Y. Yun,et al.  Automatic synthesis of extended burst-mode circuits. I.(Specification and hazard-free implementations) , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[24]  William John Bainbridge,et al.  Glitch Sensitivity and Defense of Quasi Delay-Insensitive Network-on-Chip Links , 2009, 2009 15th IEEE Symposium on Asynchronous Circuits and Systems.

[25]  Jing-Yang Jou,et al.  On-chip bus encoding for LC cross-talk reduction , 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)..

[26]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[27]  Jens Sparsø,et al.  Principles of Asynchronous Circuit Design , 2001 .

[28]  William B. Toms,et al.  Delay-insensitive, point-to-point interconnect using m-of-n codes , 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..

[29]  D.-I. Lee,et al.  Handshake protocol using return-to-zero data encoding for high performance asynchronous bus , 2003 .

[30]  Wolfgang Fichtner,et al.  Practical design of globally-asynchronous locally-synchronous systems , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[31]  Yvon Savaria,et al.  Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology , 2007, 2007 IEEE International Symposium on Circuits and Systems.