A fully planarized stacked capacitor cell for lGiga bit DRAM and beyond having three significant features has been developed. First, all the lithograpluc processes were performed on the planarized surface to achieve enough margin. Second, the patterns in critical layers were arranged to be suitable for alternating Phase Shift Mask(PSM). Third, deep contact hole resulting from introducing global planarization was adopted in a reasonable size. The cell area of 0.26um2 (0.36 x 0.72~) can be fabricated with a KrF excimer stepper using five alternating PSMs and two half tone PSMs. 1 nt rod ucti o n DRAM process development has been hghly depend on the development of lithographic technologies. But optical lithography is now facing severe problems such as wavelength limitation and insufficient overlay accuracy. Moreover, the steps between cell array and peripheral circuit area become serious problem more and more to perform DRAM process because the cell capacitance has to be maintained in each generation. The steps require a large depth of focus (DOF), restrict a design rule scaling, and also make etching of first metal layer very difficult. As a result, the chip size will be larger. To overcome the above problems, we have selected photo-lithography-fiiendly technology which means straight line and space pattern, fully planarized surface, and adopting alternating PSM. We also used a self aligned contact (SAC) technology to achieve 8F2 cell size. The fully planarized cells were reported, but they used larger cell size and relaxed design A global planarization is very attractive, but has disadvantage, which is deep and hence high aspect ratio (HAR) contact hole. We have fabricated and confumed contact resistance and junction leakage with HAR contact hole necessitated by global planarization after capacitor formation in 0.1 Sum rule. This paper describes a novel DRAM cell concept and fabrication process in 0.18~ rule with HAR contact for the fxst time.