Influence of quantization on the bit-error performance of turbo-decoders

Turbo-codes are under consideration for third generation mobile communication systems. For any implementation of a turbo-decoder a fixed-point representation is mandatory. Usually, the bit-width of a fixed-point implementation has to be traded off versus its decoding performance. Past approaches towards a fixed-point representation show a degradation in performance. In this paper we apply a novel quantization methodology on turbo-decoders with (Max-)Log-MAP component decoders and present simulation results for both an AWGN and a Rayleigh fading channel model. The new quantization scheme leads to fixed-point implementations that do not degrade the bit-error performance. Under certain conditions it can even be slightly improved.

[1]  Patrick Robertson,et al.  Optimal and sub-optimal maximum a posteriori algorithms suitable for turbo decoding , 1997, Eur. Trans. Telecommun..

[2]  P. Höher.  New Iterative ("Turbo") Decoding Algorithms. , 1997 .

[3]  William J. Ebel,et al.  Turbo code implementation issues for low latency, low power applications , 1999 .

[4]  Keshab K. Parhi,et al.  VLSI implementation issues of TURBO decoder design for wireless applications , 1999, 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461).

[5]  Paul H. Siegel,et al.  VLSI architectures for metric normalization in the Viterbi algorithm , 1990, IEEE International Conference on Communications, Including Supercomm Technical Sessions.

[6]  Patrick Schaumont,et al.  A methodology and design environment for DSP ASIC fixed point refinement , 1999, DATE '99.

[7]  John Cocke,et al.  Optimal decoding of linear codes for minimizing symbol error rate (Corresp.) , 1974, IEEE Trans. Inf. Theory.

[8]  A. Glavieux,et al.  Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1 , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[9]  Massimo Ruo Roch,et al.  VLSI architectures for turbo codes , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Norbert Wehn,et al.  Implementation aspects of turbo-decoders for future radio applications , 1999, Gateway to 21st Century Communications Village. VTC 1999-Fall. IEEE VTS 50th Vehicular Technology Conference (Cat. No.99CH36324).

[11]  Sergio Benedetto,et al.  Design of parallel concatenated convolutional codes , 1996, IEEE Trans. Commun..

[12]  Francky Catthoor,et al.  Custom Memory Management Methodology , 1998, Springer US.

[13]  Gerhard Fettweis,et al.  Comparison of different turbo decoder realizations for IMT-2000 , 1999, Seamless Interconnection for Universal Services. Global Telecommunications Conference. GLOBECOM'99. (Cat. No.99CH37042).

[14]  R. Cmar,et al.  A methodology and design environment for DSP ASIC fixed point refinement , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[15]  Yufei Wu,et al.  The influence of quantization and fixed point arithmetic upon the BER performance of turbo codes , 1999, 1999 IEEE 49th Vehicular Technology Conference (Cat. No.99CH36363).