Timing accuracy enhancement by a new calibration scheme for multi-Gbps ATE

The ever increasing data rate of high speed I/Os has required higher test timing accuracy. In order to keep improving ATE's edge placement accuracy, we have reviewed the traditional timing calibration methods in detail, and studied the timing error mechanism. Then we have developed a new calibration scheme to overcome the fundamental issues in some traditional calibration methods. Our main focus in This work is on the following three areas: data dependent jitter (timing error), pin-to-pin skew and calibration at DUT.

[1]  Masashi Shimanouchi.  New paradigm for signal paths in ATE pin electronics are needed for serialcom device testing , 2002, Proceedings. International Test Conference.

[2]  Chris Wagner,et al.  Device interfacing: the weakest link in the chain to break into the giga bit domain? , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[3]  Sunil K. Jain,et al.  Testing beyond EPA: TDF methodology solutions matrix , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[4]  Yi Cai,et al.  An accurate simulation model of the ATE test environment for very high speed devices , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[5]  Klaus Helmreich.  Test path simulation and characterisation , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[6]  Jie Sun,et al.  A generic test path and dut model for datacom ate , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[7]  Ulrich L. Rohde,et al.  Microwave Circuit Design Using Linear and Nonlinear Techniques: Vendelin/Microwave Circuit Design Using Linear and Nonlinear Techniques , 1990 .

[8]  Luca Sartori,et al.  The path to one-picosecond accuracy , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[9]  W. Tranter,et al.  Signals and Systems: Continuous and Discrete , 1983 .

[10]  M. Shitnanouchi.  Periodic jitter injection with direct time synthesis by SPP/sub tm/ ATE for serdes jitter tolerance test in production , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[11]  Thomas P. Warwick.  What a device interface board really costs: an evaluation of technical considerations for testing products operating in the Gigabit region , 2002, Proceedings. International Test Conference.

[12]  David E. McFeely.  The process and challenges of a high-speed DUT board project , 2002, Proceedings. International Test Conference.