Experimental performance of an ATM-based buffered hyperplane CMOS-SEED smart pixel array

An ATM-based buffered HyperPlane smart pixel array (SPA) utilizing the Hybrid CMOS-SEED technology has been designed, fabricated, and tested. Multiple quantum well p-i-n photodiodes (SEEDs) are used as the optoelectronic interface in the SPA. The SPA consists of a 4 X 9 array of smart pixels comprised of 4 parallel ATM node channels. The chip fabricated is an experimental version extensible to a 256 X 256 array for implementing an ATM-based HyperPlane switching architecture on a free space optical backplane. Experimental performance of the SPA is presented.

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