Buffer Analysis for Complete Application Graphs

As already shown in Chapter 6, buffer size determination is an important step in system level design of image processing applications because it helps to improve throughput by avoiding external memories. Furthermore, it is possible to reduce power dissipation and chip sizes and thus costs. Consequently, a buffer analysis technique based on simulation has been presented in the previous chapter that can be applied to arbitrary scheduling strategies. By this means, two different memory mappings, expressed in different memory models, have been compared. Whereas the first one uses a rectangular array structure, the second performs linearization in production order. As a result, it could be shown that both strategies have their advantages and drawbacks and that high-speed applications requiring parallel processing are best covered by the linearized buffer model.

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