Enabling Hybrid PCM Memory System with Inherent Memory Management

Replacing the traditional volatile main memory, e.g., DRAM, with a non-volatile phase change memory (PCM) has become a possible solution to reduce the energy consumption of computing systems. To further reduce the bit cost of PCM, the development trend of PCM goes from single-level-cell (SLC) the multi-level-cell (MLC) technology. However, the worse endurance and the intolerable long write latency hinder a MLC PCM from being used as the main memory of computing systems. In this work, we propose a memory management design to facilitate enabling the use of hybrid PCMas main memory to achieve a better trade-off between the cost and the performance of PCM-based computing systems, where the hybrid PCM is composed of SLC PCM and MLC PCM. In particular, the proposed design can be seamlessly integrated into the inherent memory management of modern operation systems without additional hardware components. The evaluation results show that the proposed design over a hybrid PCM can improve the average read/write performance for almost 10 times and extend the lifetime for more than 32 times, compared to systems with pure MLC PCM.

[1]  Norman P. Jouppi,et al.  FREE-p: Protecting non-volatile memory against both hard and soft errors , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[2]  Vijayalakshmi Srinivasan,et al.  Scalable high performance main memory system using phase-change memory technology , 2009, ISCA '09.

[3]  Tei-Wei Kuo,et al.  Improving PCM Endurance with a Constant-Cost Wear Leveling Design , 2016, ACM Trans. Design Autom. Electr. Syst..

[4]  Karin Strauss,et al.  Use ECP, not ECC, for hard failures in resistive memories , 2010, ISCA.

[5]  Onur Mutlu,et al.  Architecting phase change memory as a scalable dram alternative , 2009, ISCA '09.

[6]  Tei-Wei Kuo,et al.  Marching-Based Wear-Leveling for PCM-Based Storage Systems , 2015, TODE.

[7]  Edwin Hsing-Mean Sha,et al.  Loop scheduling optimization for chip-multiprocessors with non-volatile main memory , 2012, 2012 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

[8]  Tei-Wei Kuo,et al.  A light-weighted software-controlled cache for PCM-based main memory systems , 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[9]  Vijayalakshmi Srinivasan,et al.  Enhancing lifetime and security of PCM-based Main Memory with Start-Gap Wear Leveling , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[10]  Moinuddin K. Qureshi,et al.  Morphable memory system: a robust architecture for exploiting multi-level phase change memories , 2010, ISCA.

[11]  Marco Cesati,et al.  Understanding the Linux Kernel, Third Edition , 2005 .

[12]  Sangsoo Park,et al.  A Hybrid PRAM and STT-RAM Cache Architecture for Extending the Lifetime of PRAM Caches , 2013, IEEE Computer Architecture Letters.

[13]  Hsien-Hsin S. Lee,et al.  Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping , 2010, ISCA.

[14]  Yi He,et al.  Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation , 2010, Design Automation Conference.

[15]  Yuan Xie,et al.  AdaMS: Adaptive MLC/SLC phase-change memory design for file storage , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[16]  Jun Yang,et al.  A durable and energy efficient main memory using phase change memory technology , 2009, ISCA '09.