Negative-Bias Temperature Instability in Gate-All-Around Silicon Nanowire MOSFETs: Characteristic Modeling and the Impact on Circuit Aging

In this paper, the negative-bias temperature instability (NBTI) in p-type gate-all-around silicon nanowire MOSFETs (SNWTs) is investigated for circuit aging analysis. Several important features of NBTI in SNWTs are discussed, including the impacts of 2-D hydrogen diffusion, the nonuniform temperature profile caused by self-heating effects, the multiple crystallographic orientations of nanowire channel surface, the gate-trimming process-induced additional trapping effects, and the impacts of oxide hole trapping. A predictive NBTI model for SNWTs is proposed and adopted in circuit simulation to evaluate the performance degradations of typical logic and analog circuits, such as inverter, static random access memory cell, ring oscillator, and current mirror. Without considering other indirect factors, the results indicate that the performance degradation directly due to NBTI alone is relatively small, i.e., within the range of less than 8% degradation for the typical circuits simulated. However, the NBTI behavior in SNWTs is sensitive to process variations, which cause enhanced variability problem by inducing time-dependent threshold voltage fluctuations.

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