Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993

Part 1 Organization, synthesis and modelling: VLSI programming of a modulo-N counter with constant response time and constant power, K. van Berkel linear test times for delay-insensitive circuits - a compilation strategy, M. Roncken and R. Saeijs self-timed architecture of a reduced instruction set computer, I. David, et al self-timed fully pipelined multipliers, O. Salomon and H. Klar. Part 2 Theory and specification: normal form in a delay-insensitive algebra, R. Broenboom, et al synthesis of asynchronous control circuits from symbolic signal transition graphs, A.V. Yakolev, et al hazard-free asynchronous circuit synthesis, M.L. Yu, and P.A. Subrahmanyam automated synthesis of asynchronous interface circuits, L. Lavagno and A. Sangiovanni-Vincentelli implementing a stack as a delay-insensitive circcuit, M.B. Josephs and J.T. Udding solving a mutual exclusion problem with the RGD arbiter, J.C. Ebergen, et al. Part 3 Engineering practice: asynchronous multipliers as combinational handshake circcuits, J. Haans, et al design of self-timed multipliers - a comparison, J. Sparso, et al a CMOS VLSI implementation of an asynchronous ALU, J.D. Garside automatic synthesis of fast compact asynchronous control circuits, A. Davis, et al characterization and evaluation of a complied asynchronous IC, K. van Berkel et al.