Optimization of circuit partitioning in VLSI through classification algorithms

In order to build complex digital logic circuits it is often essential to sub-divide multi million transistors design into manageable pieces. Circuit partitioning in VLSI, is one of the major area of research. There are many existing diverse algorithm to partition the circuit into sub circuits. This paper aims at circuit partitioning using two classification algorithms Decision Tree Algorithm and K-Nearest Neighbors Algorithm. These two algorithms were tested on a 3-bit Priority Encoder and a 4×2 SRAM sample circuits and implemented using VHDL. The tested result shows that the K-Nearest Neighbor algorithm yields better subcircuits than the Decision Tree Algorithm.