Spacer based self-aligned multiple patterning (SAMP) techniques potentially allow us to scale integrated circuits down to sub-10nm half pitch with no need of EUV lithography. In this paper, we shall present a general analysis of technological merits, process complexity and costs of various SAMP techniques. It is shown that some SAMP techniques such as self-aligned quadruple/sextuple patterning (SAQP/SASP) are more capable of increasing the pattern density, while self-aligned triple patterning (SATP) is more beneficial to reducing process complexity by allowing quasi-2D IC design and requiring fewer masks. Besides their different scaling/resolution capability and process challenges, each SAMP technique is accompanied with unique characteristics of CD uniformity (CDU) and line-width roughness (LWR), which indicates their application areas and the related IC design/fabrication methodologies vary significantly by industry segment. Process costs of various self-aligned multiple patterning schemes are calculated, which show that within the common resolution capability, SATP technique is the most cost effective while the EUV+SADP approach only offers limited benefits.
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