On the effects of test compaction on defect coverage

We study the effects of test compaction on the defect coverage of test sets for modeled faults. Using a framework proposed earlier, defects are represented by surrogate faults. Within this framework, we show that the defect coverage does not have to be sacrificed by test compaction, if the test set is computed using appropriate test generation objectives. Moreover, two test sets, one compacted and one non-compacted, generated using the same test generation objectives, typically have similar defect coverages, even if the compacted one is significantly smaller than the uncompacted one. Test generation procedures and experimental results to support these claims are presented.

[1]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[2]  S. Reddy,et al.  COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[3]  Michael H. Schulz,et al.  SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  R. L. Wadsack,et al.  Fault modeling and logic simulation of CMOS and MOS integrated circuits , 1978, The Bell System Technical Journal.

[5]  Mark W. Levi,et al.  CMOS Is Most Testable , 1981, International Test Conference.

[6]  M. Ray Mercer,et al.  On efficiently and reliably achieving low defective part levels , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[7]  Edward J. McCluskey,et al.  An experimental chip to evaluate test techniques experiment results , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[8]  Irith Pomeranz,et al.  On compacting test sets by addition and removal of test vectors , 1994, Proceedings of IEEE VLSI Test Symposium.

[9]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[10]  Irith Pomeranz,et al.  COMPACTEST: a method to generate compact test sets for combinational circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  M. Ray Mercer,et al.  On the decline of testing efficiency as fault coverage approaches 100% , 1995, Proceedings 13th IEEE VLSI Test Symposium.