Design of Down-Sampling Processors for Radio Communications

This paper deals with design and implementation of digital filter processors to be used as down-samplers in wireless transceivers. We consider a homodyne direct conversion and propose an improved method to specify each stage of the cascade structure. The proposed scheme results in a globally compact implementation. The method is detailed for DECT standard and illustrated by a fixed point FPGA based implementation.

[1]  Mitsuo Makimoto,et al.  Homodyne receiver technology for small and low-power consumption mobile communications equipment , 1995, Proceedings of ISSE'95 - International Symposium on Signals, Systems and Electronics.

[2]  H. Khorramabadi,et al.  Baseband filters for IS-95 CDMA receiver applications featuring digital automatic frequency tuning , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[3]  C. Sidney Burrus,et al.  Multirate filter designs using comb filters , 1984 .

[4]  Mohamed I. Elmasry,et al.  Low-power design of decimation filters for a digital IF receiver , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[5]  Khaled Grati,et al.  Design and implementation of cascade decimation filter for radio communications , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[6]  A. Rofougaran,et al.  The future of CMOS wireless transceivers , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[7]  Hannu Tenhunen,et al.  A fifth-order comb decimation filter for multi-standard transceiver applications , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).