OPTIMAL LOGIC SYNTHESIS OF COMBINATIONAL CIRCUITS USING K-LUT FPGA

Abstract Determining if a given arbitrary, wide function can be implemented by a programmable logic block, is unfortunately, in general, a very difficult problem, called the Boolean matching problem. We introduce a novel implemented algorithm able to map for performance combinational networks using k -LUT based FPGAs. We consider in this paper delay optimum and area optimal k-LUT FPGA mapping algorithms and compare them against a newly developed and recently improved algorithm.

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