Characterization of an LVDS Link in 28 nm CMOS for Multi-Purpose Pattern Recognition

This paper presents the characterization of an input/output interface circuit designed for multi-purpose pattern recognition applications compatible with low-voltage fully differential signaling (LVDS) standard. The driver and receiver circuits described in this work has been designed and fabricated in a 28 nm CMOS technology. The prototype chip has been mounted on a printed circuit board with physical characteristics similar to the real application case and fully validated up to 1 Gb/s with input random patterns.

[1]  J. Silva-Martinez,et al.  Low-voltage low-power LVDS drivers , 2005, IEEE Journal of Solid-State Circuits.

[2]  Giovanni Calderini,et al.  AM06: the Associative Memory chip for the Fast TracKer in the upgraded ATLAS detector , 2017 .

[3]  Young-Hyun Jun,et al.  0.37mW/Gb/s low power SLVS transmitter for battery powered applications , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[4]  Valentino Liberali,et al.  A new XOR-based Content Addressable Memory architecture , 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

[5]  Ted H. Szymanski,et al.  Low power high speed I/O interfaces in 0.18 /spl mu/m CMOS , 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.

[6]  Francesco De Canio,et al.  Design of LVDS driver and receiver in 28 nm CMOS technology for Associative Memories , 2017, 2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST).

[7]  Takashi Kubota,et al.  A low-power and high-density Associative Memory in 28 nm CMOS technology , 2017, 2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST).

[8]  A. Tajalli,et al.  A Slew Controlled LVDS Output Driver Circuit in 0.18 $\mu$m CMOS Technology , 2009, IEEE Journal of Solid-State Circuits.