Compressed Bit Fail Maps for Memory Fail Pattern Classification

Process optimization in a manufacturing environment for dynamic random access devices (DRAMS) can be improved using fail bit maps in production. Since fail bit maps for 64 Mbit, 256 Mbit and 1 Gbit are quite huge, it is difficult to generate, store and analyze these maps in a manufacturing environment. This paper presents a new scheme for generating compressed bit fail maps during test or from full bit fail maps with minimum loss of fail pattern information. Construction of the special compression scheme for a typical memory array with typical fail patterns will be shown. The described method has been successfully implemented for a 64 Mbit DRAM in a manufacturing environment compressing the bit fail maps to 2 kBit, allowing classification of 13 fail types.

[1]  Dhiraj K. Pradhan,et al.  Integrated Circuit Manufacturability , 1998 .

[2]  Ad J. van de Goor,et al.  Semiconductor manufacturing process monitoring using built-in self-test for embedded memories , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[3]  Wojciech Maly,et al.  Failure analysis of high-density CMOS SRAMs: using realistic defect modeling and I/sub DDQ/ testing , 1993, IEEE Design & Test of Computers.

[4]  J. Voilrath.  Tutorial: characterizing SDRAMs , 1999, Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing.

[5]  A. H. Landzberg,et al.  Microelectronics manufacturing diagnostics handbook , 1993 .