Robust power management in the IBM z13

The power management strategy adopted for the IBM z13™ processor chip (referred to as the CP or Central Processor chip) is guided by three basic principles: (a) controlling the peak power consumption by setting a realistic limit on the so-called thermal design power or thermal design point (TDP) driven by customer workloads and maximum-power stress microbenchmarks; (b) reduction of the voltage margin by using a novel dynamic guard-banding technique; and (c) the creation of a rich new set of fine-grained, time-synchronized sensors that track performance, power, temperature, and power management behavior for a running machine. A prime requirement of the power management architecture is that the efficient control mechanisms be designed in such a manner that the high standards of IBM z Systems™ application performance and reliability be maintained without any compromise. In this paper, we describe the key features constituting the z13 CP robust power management architecture and design that meet the stipulated objectives.

[1]  Soraya Ghiasi,et al.  A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  Matthew M. Ziegler,et al.  IBM z13 circuit design and methodology , 2015, IBM J. Res. Dev..

[3]  S. Naffziger,et al.  Power and temperature control on a 90-nm Itanium family processor , 2006, IEEE Journal of Solid-State Circuits.

[4]  Ricardo Bianchini,et al.  Power and energy management for server systems , 2004, Computer.

[5]  Lizy Kurian John,et al.  AUDIT: Stress Testing the Automatic Way , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

[6]  Markus M. Helms,et al.  The IBM z13 multithreaded microprocessor , 2015, IBM J. Res. Dev..

[7]  Pradip Bose,et al.  Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

[8]  Eduard Ayguadé,et al.  A Systematic Methodology to Generate Decomposable and Responsive Power Models for CMPs , 2013, IEEE Transactions on Computers.

[9]  Bishop Brock,et al.  Active Guardband Management in Power7+ to Save Energy and Maintain Reliability , 2013, IEEE Micro.

[10]  Gary D. Carpenter,et al.  Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor , 2013, International Symposium on Low Power Electronics and Design (ISLPED).

[11]  Bishop Brock,et al.  Adaptive energy-management features of the IBM POWER7 chip , 2011, IBM J. Res. Dev..

[12]  Pradip Bose,et al.  Abstraction and microarchitecture scaling in early-stage power modeling , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[13]  Jack Doweck,et al.  Inside Intel® Core microarchitecture , 2006, 2006 IEEE Hot Chips 18 Symposium (HCS).

[14]  Dan Bouvier,et al.  AMD "kabini" APU SOC , 2013, 2013 IEEE Hot Chips 25 Symposium (HCS).

[15]  Freeman L. Rawson,et al.  EnergyScale for IBM POWER6 microprocessor-based systems , 2007, IBM J. Res. Dev..

[16]  Michael S. Floyd,et al.  Voltage droop reduction using throttling controlled by timing margin feedback , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[17]  Bishop Brock,et al.  Accurate Fine-Grained Processor Power Proxies , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

[18]  Alon Naveh,et al.  Power management architecture of the 2nd generation Intel® Core microarchitecture, formerly codenamed Sandy Bridge , 2011, IEEE Hot Chips Symposium.

[19]  BosePradip,et al.  Adaptive energy-management features of the IBM POWER 7 chip , 2011 .

[20]  P.J. Restle,et al.  Timing uncertainty measurements on the Power5 microprocessor , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[21]  Xiaorui Wang,et al.  Power capping: a prelude to power shifting , 2008, Cluster Computing.

[22]  Meeta Sharma Gupta,et al.  Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.