Fin Shape Impact on FinFET Leakage With Application to Multithreshold and Ultralow-Leakage FinFET Design

FinFETs have emerged as the solution to short channel effects at the 22-nm technology node and beyond. Previously, there have been few studies on the impact of fin cross section shape on transistor leakage. We show for the first time that fin shape significantly impacts transistor leakage in bulk tri-gate nFinFETs with thin fins when the fin body doping profile is optimized to minimize leakage. We show that a triangular fin reduces leakage current by 70% over a rectangular fin with the same base fin width. We describe how fin shape can be used to implement multithreshold nFinFETs without increasing chip area consumption. We also describe how by combining triangular fins with existing gate-source/drain underlap multithreshold techniques, it is possible to design ultralow-power nFinFETs with less than 1 pA/μm leakage current while maintaining high performing ION/IOFF, threshold voltage, and subthreshold swing.

[1]  Andrew R. Brown,et al.  Impact of Metal Gate Granularity on Threshold Voltage Variability: A Full-Scale Three-Dimensional Statistical Simulation Study , 2010, IEEE Electron Device Letters.

[2]  George Varghese,et al.  A 22nm IA multi-CPU and GPU System-on-Chip , 2012, 2012 IEEE International Solid-State Circuits Conference.

[3]  A. Schenk Rigorous theory and simplified model of the band-to-band tunneling in silicon , 1993 .

[4]  Volkan Kursun,et al.  Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[5]  Jeffrey Bokor,et al.  Investigation of Gate-Induced Drain Leakage (GIDL) Current in Thin Body Devices: Single-Gate Ultra-Thin Body, Symmetrical Double-Gate, and Asymmetrical Double-Gate MOSFETs , 2003 .

[6]  Rita Rooyackers,et al.  Multi-gate devices for the 32 nm technology node and beyond , 2008 .

[7]  J. Bude,et al.  MOSFET modeling into the ballistic regime , 2000, 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502).

[8]  Meng-Hsueh Chiang,et al.  Performance advantage and energy saving of triangular-shaped FinFETs , 2013, 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

[9]  D. Varghese,et al.  Device Design and Optimization Considerations for Bulk FinFETs , 2008, IEEE Transactions on Electron Devices.

[11]  C. Auth,et al.  A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[12]  Andrew R. Brown,et al.  Statistical variability and reliability in nanoscale FinFETs , 2011, 2011 International Electron Devices Meeting.

[13]  Bing J. Sheu,et al.  Enabling circuit design using FinFETs through close ecosystem collaboration , 2013, 2013 Symposium on VLSI Technology.

[14]  Volkan Kursun,et al.  Multi-Threshold Voltage FinFET Sequential Circuits , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  P. Oldiges,et al.  Channel doping impact on FinFETs for 22nm and beyond , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[16]  E. Suzuki,et al.  Cross-Sectional Channel Shape Dependence of Short-Channel Effects in Fin-Type Double-Gate Metal Oxide Semiconductor Field-Effect Transistors , 2004 .

[17]  E.. Baravelli,et al.  Impact of Line-Edge Roughness on FinFET Matching Performance , 2007, IEEE Transactions on Electron Devices.

[18]  G. Curello,et al.  A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications , 2012, 2012 International Electron Devices Meeting.