A high-level dynamic-error model of a pipelined analog-to-digital converter

The paper presents a fast and accurate high-level model of a pipelined analog-to-digital converter implemented in MATLAB. Mechanisms causing dynamic errors, such as the settling time of a slew-rate-limited amplifier, are analyzed and parameters to model these identified. All parameters are associated with actual physical properties and all simulations are validated by comparison to measured data in both time and frequency domains.

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