A 5-32 bit decoder for application in a crossbar switch

A novel voltage state multiple input NOR gate has been designed and tested for use as the basic gate in a 5-32 b parallel-input decoder. Two versions of this NOR gate are presented, one with a single output and one with a selectable output. The combination of the two types of NOR gate makes it possible to construct a 5-32 b decoder with considerably less gate current than would be required if it were constructed in other logic families. Since only a single gate current is required by each NOR gate and because only 12 NOR gates are needed to build the full decoder, a clock with a peak current level of only 6 mA is sufficient to power all of the decoder's 72 constituent superconducting quantum interference devices (SQUIDs). The decoder also occupies a small area compared with other designs. The authors review critical design issues of the NOR gates, and present low-speed and high-speed results of subblocks of the full 5-32 b decoder.<<ETX>>