Design of a faithful LNS interpolator

A design is given for a quadratic interpolator needed by the logarithmic number system (LNS). Unlike previous LNS designs that have attempted to produce results consistently better than a floating-paint representation of the same word size (32 bits), the design goal is to minimize memory requirements and system complexity, at the expense of a slight increase in approximation error. Simulation results have shown this goal causes only a modest impact on overall accuracy, but the memory savings are significant. Despite a slight increase in error compared to prior LNS implementations, on average, the error is still less than conventional number representations satisfying the IEEE-754 standard. Proposed applications for the interpolator include multimedia, signal processing, graphics and reconfigurable computing.

[1]  David Lewis.  114 MFLOPS logarithmic number system arithmetic unit for DSP applications , 1995 .

[2]  Tomio Kurokawa,et al.  A Fast and Simple Method for Curve Drawing-A New Approach Using Logarithmic Number System- , 1991 .

[3]  J. J. Cupal,et al.  On the cost effectiveness of logarithmic arithmetic for backpropagation training on SIMD processors , 1997, Proceedings of International Conference on Neural Networks (ICNN'97).

[4]  Andrew S. Noetzel.  An Interpolating Memory Unit for Function Evaluation: Analysis and Design , 1989, IEEE Trans. Computers.

[5]  Mark G. Arnold,et al.  Redundant Logarithmic Arithmetic , 1990, IEEE Trans. Computers.

[6]  Mark G. Arnold,et al.  Unrestricted faithful rounding is good enough for some LNS applications , 2001, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001.

[7]  Mary Jane Irwin,et al.  The logarithmic number system for strength reduction in adaptive filtering , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[8]  Z. Dahan,et al.  A 32 b 64-matrix parallel CMOS processor , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[9]  Vassilis Paliouras,et al.  Logarithmic Number System for Low-Power Arithmetic , 2000, PATMOS.

[10]  Jirí Kadlec,et al.  Arithmetic on the European Logarithmic Microprocessor , 2000, IEEE Trans. Computers.

[11]  장훈,et al.  [서평]「Computer Organization and Design, The Hardware/Software Interface」 , 1997 .

[12]  Fred J. Taylor,et al.  A 20 Bit Logarithmic Number System Processor , 1988, IEEE Trans. Computers.

[13]  Earl E. Swartzlander,et al.  Sign/Logarithm Arithmetic for FFT Implementation , 1983, IEEE Transactions on Computers.

[14]  Donald J. Patterson,et al.  Computer organization and design: the hardware-software interface (appendix a , 1993 .

[15]  Debjit Das Sarma,et al.  Faithful bipartite ROM reciprocal tables , 1995, Proceedings of the 12th Symposium on Computer Arithmetic.

[16]  Mark G. Arnold,et al.  Comments on "An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System'' , 1992, IEEE Trans. Computers.

[17]  Guido D. Salvucci,et al.  Ieee standard for binary floating-point arithmetic , 1985 .

[18]  M. G. Arnold.  A pipelined LNS ALU , 2001, Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems.

[19]  Rui-Lin Chen,et al.  Pipelined Computation of Very Large Word-Length LNS Addition/Subtraction with Polynomial Hardware Cost , 2000, IEEE Trans. Computers.

[20]  H. Henkel.  Improved addition for the logarithmic number system , 1989, IEEE Trans. Acoust. Speech Signal Process..

[21]  Mark G. Arnold,et al.  Arithmetic Co-Transformations in the Real and Complex Logarithmic Number Systems , 1998, IEEE Trans. Computers.

[22]  Harvey F. Silverman,et al.  Performing Log-Scale Addition on a Distributed Memory MIMD Multicomputer with Reconfigurable Computing Capabilities , 1995, International Conference on Parallel Processing.

[23]  Jeffrey H. Lang,et al.  Integrated-Circuit Logarithmic Arithmetic Units , 1985, IEEE Transactions on Computers.

[24]  David M. Lewis.  Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit , 1994, IEEE Trans. Computers.

[25]  N. Kingsbury,et al.  Digital filtering using logarithmic arithmetic , 1971 .

[26]  David M. Lewis.  An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System , 1990, IEEE Trans. Computers.