Programming the data path in network processor‐based routers

There is growing interest in network processor technologies capable of processing packets at line rates. Network processors are likely to be an integral part of next generation high‐speed router and switch architectures, replacing the application‐specific integrated circuits (ASICs) that are used in routers today. In this paper, we present the design, implementation and evaluation of NetBind, a high‐performance, flexible and scalable binding tool for dynamically constructing data paths in network processor‐based routers. The methodology that underpins NetBind balances the flexibility of network programmability against the need to process and forward packets at line speeds. To support the dynamic binding of components with the minimum addition of instructions in the critical path, NetBind modifies the machine language code of components at run time. To support fast data path composition, NetBind reduces the number of binding operations required for constructing data paths to a minimum set so that binding latencies are comparable with packet forwarding times. Data paths constructed using NetBind seamlessly share the resources of the same network processor. Resources are assigned during the binding process. We compare the performance of NetBind to the MicroACE system developed by Intel and show that NetBind provides better performance in comparison to MicroACE with smaller binding overhead. The NetBind source code described and evaluated in this paper is freely available on the Web (http://www.comet.columbia.edu/genesis/netbind) for experimentation. Copyright © 2005 John Wiley & Sons, Ltd.

[1]  Steve Vinoski,et al.  CORBA: integrating diverse applications within distributed heterogeneous environments , 1997, IEEE Commun. Mag..

[2]  Yitzchak M. Gottlieb,et al.  Building a robust software-based router using network processors , 2001, SOSP.

[3]  Calton Pu,et al.  The Synthesis Kernel , 1988, Comput. Syst..

[4]  Harrick M. Vin,et al.  Start-time fair queueing: a scheduling algorithm for integrated services packet switching networks , 1996, SIGCOMM '96.

[5]  Hui Zhang,et al.  Hierarchical packet fair queueing algorithms , 1996, SIGCOMM 1996.

[6]  Eddie Kohler,et al.  The Click modular router , 1999, SOSP.

[7]  Tilman Wolf,et al.  Scheduling processing resources in programmable routers , 2002, Proceedings.Twenty-First Annual Joint Conference of the IEEE Computer and Communications Societies.

[8]  Jon Postel,et al.  Internet Protocol , 1981, RFC.

[9]  Chieh-Yih Wan,et al.  Design, implementation, and evaluation of cellular IP , 2000, IEEE Wirel. Commun..

[10]  Larry L. Peterson,et al.  Scout: a communications-oriented operating system , 1995, Proceedings 5th Workshop on Hot Topics in Operating Systems (HotOS-V).

[11]  Albert G. Greenberg,et al.  Hardware-efficient fair queueing architectures for high-speed networks , 1996, Proceedings of IEEE INFOCOM '96. Conference on Computer Communications.

[12]  John H. Hartman,et al.  Scout: A Communications-Oriented Operating System (Abstract) , 1994, OSDI.

[13]  Manojit Sarkar,et al.  Author Affiliation and Contact Information , 2007 .

[14]  Scott Shenker,et al.  Analysis and simulation of a fair queueing algorithm , 1989, SIGCOMM '89.

[15]  Douglas C. Schmidt,et al.  Applying patterns to develop extensible ORB middleware , 1999, IEEE Commun. Mag..

[16]  Michael E. Kounavis,et al.  Directions in Packet Classification for Network Processors , 2004 .

[17]  Harrick M. Vin,et al.  Start-time fair queueing: a scheduling algorithm for integrated services packet switching networks , 1997, TNET.

[18]  Nick McKeown,et al.  Packet classification on multiple fields , 1999, SIGCOMM '99.

[19]  Andrew T. Campbell,et al.  The Genesis Kernel: a programming system for spawning network architectures , 2001, IEEE J. Sel. Areas Commun..

[20]  Jean Calvignac,et al.  IBM—PowerNP Network Processor , 2003 .

[21]  Hui Zhang,et al.  Hierarchical packet fair queueing algorithms , 1996, SIGCOMM '96.

[22]  Larry Peterson,et al.  Evaluating Network Processors in IP Forwarding , 2000 .

[23]  George Varghese,et al.  Efficient fair queueing using deficit round robin , 1995, SIGCOMM '95.

[24]  Tilman Wolf,et al.  Design issues for high-performance active routers , 2001, IEEE J. Sel. Areas Commun..