3D FOWLP Integration

Fan-Out Wafer Level Packaging (FOWLP) is the most popular packaging and integration technology today. It has evolved from providing basic routing of the bare chip electrical Input/Output (I/Os) connection to a complex multi-functionality System-in-Package (SiP) integration platform. The FOWLP has the unique ability to embed the bare chip in the mold compound and provides the rerouting of either fanning-out or fanning-in of the electrical connection using the Redistribution Layer (RDL). This has helped to support the continuous shrink of the device technology nodes which requires higher electrical speed and higher density I/O connection to the main PCB board. In order to miniaturize the electrical circuit or module size, and improve the performance, multi chips are integrated on the same molded package. In this way, the interchip connections are made using the package RDL without going through the PCB. Depending on the applications, the chips can be integrated laterally or stack vertically to achieve the shortest interconnect length or smallest package size. Besides the multi-chip integration, the mold compound of the FOWLP can also be used to realize RF circuits such as high Q inductor and high frequency antenna.