A fast buffered routing tree construction algorithm under accurate delay model

Buffer insertion method plays a great role in modern VLSI design. Many buffer insertion algorithms have been proposed in recent years. However, most of them used simplified delay models to estimate interconnect and buffer delays, which may cause inferior solutions due to delay estimation errors. On the other hand, with the amount of buffers becomes larger, buffers consume more power supply. Hence it is significant to reduce the number of buffers during interconnect delay optimization. In this paper, we present a fast buffered routing tree construction algorithm under accurate delay model with consideration of buffer/wire sizing, routing obstacles and total buffer area reduction simultaneously. Experimental result shows, compared with previous Fast-RTBW (Dechu, 2004) algorithm, our algorithm gives better routing tree solutions with less than half of the buffers.

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