Grid Synchronization Phase-Locked Loop Strategy for Unbalance and Harmonic Distortion Conditions

The synthesis, design and analysis of a three-phase phase-locked loop (PLL) algorithm under grid voltage uncertainties is presented. Unlike other techniques, the proposed strategy is simple but yet, robust against unbalanced and distorted voltage conditions. The method does not rely on the symmetry of the three-phase voltages, like conventional PLL implementation techniques. Under phase lock, the reference voltage and the output voltage are in synchronism, hence they cross the zero axis at the same time. The proposed PLL implementation exploits this fact, by counting the difference between the zero crossing times of the grid voltage and the output voltage waveform, and generating an error signal proportional to this difference. This error is fed into a PI regulator which forces it to zero over time. The proposed algorithm is compared against two popular PLL techniques. Simulation and experimental results show better performance of the proposed PLL implementation in unbalanced grid voltage conditions.