论文信息 - Digital background calibration for A 14-bit 100-MS/s pipelined ADC using signal-dependent dithering

Digital background calibration for A 14-bit 100-MS/s pipelined ADC using signal-dependent dithering

A digital background calibration technique using signal-dependent dithering is proposed to correct the multiplying DAC (MDAC) gain error of a 2.5b/stage pipelined ADC. Behavioral simulation results show that, using the proposed calibration technique, the signal-to-noise-and-distortion ratio improves from 63.3 to 79.3 dB and the spurious-free dynamic range is increased from 63.9 to 96.4 dB after calibrating the first two stages, in a 14-bit 100-MS/s pipelined ADC with σ=0.2% capacitor mismatches and 60 dB non-ideal opamp gain.

Xiaoyong He | Min Cai | Zhao-Xin Xiong

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