Highly scalable parallel parametrizable architecture of the motion estimator

In this paper a parametrizable architecture of a motion estimator (ME) is presented. The ME is designed as a generic full pixel calculation module which can be adopted for different video standards. The parameters by which the ME is described allow for a variety of architecture implementations. The parameters specify the level of parallelism reflected by multiple allocation of computational resources, and the use of configurable cache memories. The obtained VHDL description of the ME module is well suited for VLSI implementation.

[1]  Peter Pirsch,et al.  VLSI architectures for video compression , 1995, Proceedings of ISSE'95 - International Symposium on Signals, Systems and Electronics.

[2]  Ming-Ting Sun,et al.  A family of vlsi designs for the motion compensation block-matching algorithm , 1989 .

[3]  Peter Pirsch,et al.  VLSI architectures for video compression-a survey , 1995, Proc. IEEE.

[4]  Peter Pirsch,et al.  Architectural approaches for video compression , 1997, Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors.

[5]  Peter Pirsch,et al.  Array architectures for block matching algorithms , 1989 .

[6]  Liang-Gee Chen,et al.  An efficient and simple VLSI tree architecture for motion estimation algorithms , 1993, IEEE Trans. Signal Process..

[7]  Michael Stegherr,et al.  Parameterizable VLSI architectures for the full-search block-matching algorithm , 1989 .