A 0.7-Microsecond Ferrite Core Memory
暂无分享,去创建一个
The design and performance of a newly developed magnetic core memory is described. A two-dimensional array organization and partial switching of toroidal cores were employed in the design of this low-power, high-speed memory. The memory features a unique combination of a current-steering diode matrix and a load-sharing magnetic switch for an economical and high-performance drive system. The operating memory has a storage capacity of 73,728 bits and executes instructions reliably up to a repetition rate of 1.47 mc. The discussion will include a description of the organization, the series-parallel delay line clock, the control of critical timing pulses, and the actual measured performance.
[1] Ernest D. Foss,et al. A 32, 000-Word Magnetic-Core Memory , 1957, IBM J. Res. Dev..
[2] G. Constantine. A Load-Sharing Matrix Switch , 1958, IBM J. Res. Dev..
[3] Charles Avery Allen,et al. A 2.18-Microsecond Megabit Core Storage Unit , 1961, IRE Trans. Electron. Comput..