Diagnosing Delay Faults in Combinational Circuits under the Ambiguous Delay Model

SUMMARY In our previous paper [9] we presented a pathtracing method of multiple gate delay fault diagnosis in combinational circuits. In this paper,we propose an improved method that uses the ambiguous delay model. This delay model makes provision for parameter variations in the manufacturing process of ICs. For the effectiveness of the current method,we propose a timed 8-valued simulation and some new diagnostic rules. Furthermore,we introduce a preparatory process that speeds up diagnosis. Also,at the end of diagnosis,additional information from the results of the preparatory process makes it possible to

[1]  Seiichiro Tani,et al.  Efficient path selection for delay testing based on partial path evaluation , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[2]  Patrick Girard,et al.  An advanced diagnostic method for delay faults in combinational faulty circuits , 1995, J. Electron. Test..

[3]  Yuzo Takamatsu,et al.  A method of generating tests for marginal delays and delay faults in combinational circuits , 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

[4]  Hiroshi Takahashi,et al.  Multiple Gate Delay Fault Diagnosis Using Test-Pairs for Marginal Delays , 1998 .

[5]  Vishwani D. Agrawal,et al.  Parallel concurrent path-delay fault simulation using single-input change patterns , 1996, Proceedings of 9th International Conference on VLSI Design.

[6]  Michael D. Ciletti,et al.  A variable observation time method for testing delay faults , 1991, DAC '90.

[7]  Nandakumar N. Tendolkar.  Analysis of Timing Failures Due to Random AC Defects in VLSI Modules , 1985, 22nd ACM/IEEE Design Automation Conference.

[8]  C. Landrault,et al.  Effectiveness of a variable sampling time strategy for delay fault diagnosis , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[9]  Michael D. Ciletti,et al.  A Simplified Six-Waveform Type Method for Delay Fault Testing , 1989, 26th ACM/IEEE Design Automation Conference.

[10]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[11]  F. Brglez,et al.  A neutral netlists of 10 combinational circuits and a target translator in FORTRAN , 1985 .