Behavioral transformations to increase noise immunity in asynchronous specifications

Noise immunity is becoming one of the most important design parameters for deep-sub-micron (DSM) technologies. Asynchronous circuits seem to be a good candidate to alleviate the problems originated by simultaneous switching noise. However, they are also more sensitive than synchronous ones to spurious signal transitions and delay variations produced by crosstalk noise. This paper addresses the problem of analyzing and synthesizing asynchronous circuits with noise immunity being the main design parameter. The techniques presented in the paper focus on crosstalk noise and tackle the problem from the behavioral point of view.

[1]  Lawrence T. Pileggi,et al.  Calculating worst-case gate delays due to dominant capacitance coupling , 1997, DAC.

[2]  Jason Cong,et al.  The new line in IC design , 1997 .

[3]  Luciano Lavagno,et al.  Decomposition and technology mapping of speed-independent circuits using Boolean relations , 1997, ICCAD 1997.

[4]  Malgorzata Marek-Sadowska,et al.  Crosstalk reduction for VLSI , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Mark Bohr Silicon trends and limits for advanced microprocessors , 1998, CACM.

[6]  Alberto L. Sangiovanni-Vincentelli,et al.  Digital sensitivity: predicting signal interaction using functional analysis , 1996, Proceedings of International Conference on Computer Aided Design.

[7]  Luciano Lavagno,et al.  The Use of Petri Nets for the Design and Verification of Asynchronous Circuits and Systems , 1998, J. Circuits Syst. Comput..

[8]  A. Sangiovanni-Vincentelli,et al.  Constraint-based channel routing for analog and mixed analog/digital circuits , 1990, ICCAD 1990.

[9]  Dennis Sylvester,et al.  Interconnect scaling: signal integrity and performance in future high-speed CMOS designs , 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

[10]  Michael Kishinevsky,et al.  Concurrent hardware : the theory and practice of self-timed design , 1993 .

[11]  Luciano Lavagno,et al.  Lazy transition systems: application to timing optimization of asynchronous circuits , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[12]  L. Gal,et al.  On-chip cross talk-the new signal integrity challenge , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

[13]  Dongsheng Wang,et al.  Post global routing crosstalk synthesis , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Kenneth L. Shepard,et al.  Global Harmony: coupled noise analysis for full-chip RC interconnect networks , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[15]  Luciano Lavagno,et al.  Decomposition and technology mapping of speed-independent circuits using Boolean relations , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[16]  D. L. Jackson,et al.  Noise in self-timed and synchronous implementations of a DSP , 1998, Proceedings RAWCON 98. 1998 IEEE Radio and Wireless Conference (Cat. No.98EX194).

[17]  Alberto Sangiovanni-Vincentelli,et al.  Digital sensitivity: predicting signal interaction using functional analysis , 1996, ICCAD 1996.

[18]  F. Dartu,et al.  Calculating worst-case gate delays due to dominant capacitance coupling , 1997, Proceedings of the 34th Design Automation Conference.

[19]  K. L. Shepard,et al.  Global harmony: coupled noise analysis for full-chip RC interconnect networks , 1997, ICCAD 1997.

[20]  Bill Lin,et al.  Modeling and synthesis of timed asynchronous circuits , 1994, EURO-DAC '94.

[21]  Luciano Lavagno,et al.  Automatic synthesis and optimization of partially specified asynchronous systems , 1999, DAC '99.

[22]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[23]  Alberto L. Sangiovanni-Vincentelli,et al.  Techniques for crosstalk avoidance in the physical design of high-performance digital systems , 1994, ICCAD.

[24]  A.L. Sangiovanni-Vincentelli,et al.  Techniques For Crosstalk Avoidance In The Physical Design Of High-performance Digital Systems , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[25]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[26]  Luciano Lavagno,et al.  Algorithms for Synthesis and Testing of Asynchronous Circuits , 1993 .

[27]  Michael Kishinevsky,et al.  Analysis of Petri Nets by Ordering Relations in Reduced Unfoldings , 1998, Formal Methods Syst. Des..

[28]  Ren-Song Tsay,et al.  An exact zero-skew clock routing algorithm , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[29]  Tam-Anh Chu,et al.  Synthesis of self-timed VLSI circuits from graph-theoretic specifications , 1987 .

[30]  Tadao Murata,et al.  Petri nets: Properties, analysis and applications , 1989, Proc. IEEE.

[31]  Kees van Berkel Beware the isochronic fork , 1992, Integr..