Noise Considerations on High Density DRAMs: Problems and Solutions

On-chip generated noise limits further miniaturization of DRAMs. The basis for consideration is a model including the effects of ohmic voltage drop and bond wire inductances. SPICE simulations are used to study the performance that results from chip architecture, circuit placement and circuit design. The results are verified by experimental data.

[1]  J. Harter,et al.  A 4 megabit dynamic RAM in submicron CMOS technology with a FOBIC trench cell , 1987 .

[2]  T. Gabara,et al.  Ground Bounce Control In Cmos Integrated Circuits , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.