A Universal Core Model for Multiple-Gate Field-Effect Transistors. Part I: Charge Model

A universal core model for multiple-gate field-effect transistors (Mug-FETs) is proposed. The proposed charge and drain current models are presented in Parts I and II, respectively. It is first demonstrated that an exact potential profile in the entire channel is not necessary for the derivation of accurate charge models in inversion-mode FETs. With application of this new concept, a universal charge model is derived for Mug-FETs by assuming an arbitrary channel potential profile, which simplifies the mathematical formulation. Thereafter, using the Pao-Sah integral, a drain current model is obtained from the charge model of Part I. The proposed model can be expressed as an explicit and continuous form for all operation regimes; therefore, it is well suited for compact modeling to support fast circuit simulations. The model shows good agreement with 2-D and 3-D numerical simulations for several multiple-gate structures, such as single-gate, double-gate, triple-gate, rectangular gate-all-around, and cylindrical gate-all-around FETs.

[1]  G. Gildenblat,et al.  PSP-based scalable compact FinFET model , 2007 .

[2]  K. Steinhubl Design of Ion-Implanted MOSFET'S with Very Small Physical Dimensions , 1974 .

[3]  R.H. Dennard,et al.  Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions , 1974, Proceedings of the IEEE.

[4]  Isabel M. Tienda-Luna,et al.  Modeling the equivalent oxide thickness of Surrounding Gate SOI devices with high-κ insulators , 2008 .

[5]  Ali M. Niknejad,et al.  BSIM-CG: A compact model of cylindrical/surround gate MOSFET for circuit simulations , 2012 .

[6]  D. Flandre,et al.  A 3-D Analytical Physically Based Model for the Subthreshold Swing in Undoped Trigate FinFETs , 2007, IEEE Transactions on Electron Devices.

[7]  C. Sah,et al.  Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors☆ , 1966 .

[8]  T.-S. Chen,et al.  Determination of the Capacitance, Inductance, and Characteristic Impedance of Rectangular Lines , 1960 .

[9]  J.J. Liou,et al.  A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs , 2007, IEEE Transactions on Electron Devices.

[10]  Marcelo Antonio Pavanello,et al.  Threshold voltage in junctionless nanowire transistors , 2011 .

[11]  F. Gamiz,et al.  Equivalent Oxide Thickness of Trigate SOI MOSFETs With High- $\kappa$ Insulators , 2009, IEEE Transactions on Electron Devices.

[12]  F. Gamiz,et al.  An Inversion-Charge Analytical Model for Square Gate-All-Around MOSFETs , 2011, IEEE Transactions on Electron Devices.

[13]  Isabelle Ferain,et al.  Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors , 2011, Nature.

[14]  Mohan Vamsi Dunga,et al.  Nanoscale CMOS modeling , 2008 .

[15]  Adelmo Ortiz-Conde,et al.  Rigorous analytic solution for the drain current of undoped symmetric dual-gate MOSFETs , 2005 .

[16]  B. Iñíguez,et al.  Continuous analytic I-V model for surrounding-gate MOSFETs , 2004, IEEE Electron Device Letters.

[17]  Christian Enz,et al.  A Design Oriented Charge-based Current Model for Symmetric DG MOSFET and its Correlation with the EKV Formalism , 2005 .

[18]  Yuan Taur,et al.  Explicit Continuous Models for Double-Gate and Surrounding-Gate MOSFETs , 2007, IEEE Transactions on Electron Devices.

[19]  Juan Bautista Roldán,et al.  An analytical model for square GAA MOSFETs including quantum effects , 2010 .

[20]  G. Ghibaudo,et al.  Semianalytical Modeling of Short-Channel Effects in Lightly Doped Silicon Trigate MOSFETs , 2008, IEEE Transactions on Electron Devices.

[21]  Y. Taur,et al.  A continuous, analytic drain-current model for DG MOSFETs , 2004 .

[22]  Chenming Hu,et al.  Modeling Advanced FET Technology in a Compact Model , 2006, IEEE Transactions on Electron Devices.

[23]  Mansun Chan,et al.  A Charge-Based Model for Long-Channel Cylindrical Surrounding-Gate MOSFETs From Intrinsic Channel to Heavily Doped Body , 2008, IEEE Transactions on Electron Devices.

[24]  Denis Flandre,et al.  Compact model for highly-doped double-gate SOI MOSFETs targeting baseband analog applications , 2007 .

[25]  Feng Liu,et al.  Effects of body doping on threshold voltage and channel potential of symmetric DG MOSFETs with continuous solution from accumulation to strong-inversion regions , 2009 .

[26]  Y. Chen,et al.  A Comparative Study of Double-Gate and Surrounding-Gate MOSFETs in Strong Inversion and Accumulation Using an Analytical Model , 2001 .

[27]  Jon Cartwright Intel enters the third dimension , 2011 .

[28]  Jong-Tea Park,et al.  Pi-Gate SOI MOSFET , 2001, IEEE Electron Device Letters.

[29]  Y. Taur,et al.  A Unified Analytic Drain–Current Model for Multiple-Gate MOSFETs , 2008, IEEE Transactions on Electron Devices.

[30]  Jean-Pierre Colinge,et al.  Multiple-gate SOI MOSFETs , 2004 .

[31]  Yuan Taur An analytical solution to a double-gate MOSFET with undoped body , 2000, IEEE Electron Device Letters.