Fabrication technology for lead-alloy Josephson devices for high-density integrated circuits

Fabrication technology for lead‐alloy Josephson devices was evaluated from the viewpoint of application to large‐scale integrated circuits. Metal and insulating layers used in the circuits were evaluated, and optimization of techniques for deposition or formation of these layers was investigated. Metallization of the Pb‐In‐Au base electrode and the Pb‐Bi counterelectrode was studied in terms of optimizing the deposited films, to improve the reliability of junction electrodes. The formation of the oxide barrier was studied by in situ ellipsometry. SiOx deposited in oxygen was developed as the insulation layer with less defect density than conventional SiO. A liftoff technique using toluene soaking was developed, and patterns with a minimum line width of 2 μm were consistently reproduced. The characteristics of each element in the circuits were evaluated for test vehicles. For the junction, the following items were evaluated: controllability of the critical current Ic, junction quality, Ic uniformity, junct...

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