Bandpass Delta-Sigma Modulators for Radio Receivers

This thesis concerns discrete-time (DT) bandpass (BP) ∆Σ modulators targeted for intermediate frequency (IF) analog-to-digital (A/D) conversion in radio receivers. The receiver architecture adopted has to be capable of operating with different radio frequencies, channel bandwidths, and modulation techniques. This is necessary in order to achieve an extensive operating area and the possibility of utilizing a local mobile phone standard or a standard suitable for a specific service. The digital IF receiver is a good choice for a multi-mode and multi-band mobile phone receiver, because the signal demodulation and channel filtering are performed in the digital domain. This increases the flexibility of the receiver and relieves the design of the baseband part, but an A/D conversion with high dynamic range and low power dissipation is required. BP ∆Σ modulators are capable of converting a high-frequency narrow band signal and are therefore suitable for signal digitization in an IF receiver. First, the theory of BP ∆Σ modulators is introduced. It has been determined that resonators are the most critical circuit blocks in the implementation of a high performance BP ∆Σ modulator. Different DT resonator topologies are studied and a doubledelay (DD) resonator is found to be the best candidate for a high quality resonator. A new DD switched-capacitor (SC) resonator structure has been designed. Furthermore, two evolution versions of the designed SC resonator are presented and their nonidealities are analyzed. The three designed DD SC resonator structures are a main point of the thesis, together with the experimental results. Five different DT BP ∆Σ modulator circuit structures have been implemented and measured. All three of the designed SC resonators are used in the implemented circuits. The experimental work consists of both single-bit and multi-bit structures, as well as both single-loop and cascade architectures. The circuits have been implemented with a 0.35μm (Bi)CMOS technology and operate with a 3.0V supply. The measured maximum signal-to-noise-and-distortion ratios (SNDRs) are 78dB over 270kHz (GSM), 75dB over 1.25MHz (IS-95), 69dB over 1.762MHz (DECT), and

[1]  Lucien Breems,et al.  Continuous-Time Sigma-Delta Modulation for IF A/D Conversion in Radio Receivers , 2001 .

[2]  Thomas Burger,et al.  A 13.5mW, 185 MSample/s ΔΣ-modulator for UMTS/GSM dual-standard IF reception , 2001 .

[3]  Saska Lindfors,et al.  A low-voltage single-Opamp 4th-order band-pass /spl Delta//spl Sigma/-modulator , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[4]  Y. Akazawa,et al.  Jitter analysis of high-speed sampling systems , 1990 .

[5]  Y. J. Park,et al.  A new charge pump without degradation in threshold voltage due to body effect [memory applications] , 2000, IEEE Journal of Solid-State Circuits.

[6]  Todd L. Brooks,et al.  A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR , 1997 .

[7]  W. Snelgrove,et al.  Design and implementation of a tunable 40 MHz-70 MHz Gm-C bandpass /spl Delta//spl Sigma/ modulator , 1997 .

[8]  Kari Halonen,et al.  Circuit Techniques for Low-Voltage and High-Speed A/D Converters , 2002 .

[9]  M. S. Kappes,et al.  A versatile 1.75mW CMOS continuous–time delta–sigma ADC with 75dB dynamic range for wireless applications , 2002 .

[10]  Franco Maloberti,et al.  Design considerations on low-voltage low-power data converters , 1995 .

[11]  P. F. Ferguson,et al.  A 4 TH-ORDER BANDPASS SIGMA-DELTA MODULATOR Parameter Symbol , 2004 .

[12]  Saska Lindfors,et al.  A double-sampling SC-resonator for low voltage bandpass /spl Delta//spl Sigma/-modulators , 2002 .

[13]  Behzad Razavi,et al.  Design considerations for direct-conversion receivers , 1997 .

[14]  F. Maloberti,et al.  A 30-mW 10.7-MHz pseudo-N-path sigma-delta band-pass modulator , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[15]  David A. Johns,et al.  Analog Integrated Circuit Design , 1996 .

[16]  S. Lindfors,et al.  A novel technique for noise reduction in CMOS subsamplers , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[17]  Richard Schreier,et al.  Bandpass sigma-delta modulation , 1989 .

[18]  E. J. V. D. Zwan,et al.  A 10.7 MHz IF-to-baseband ΣΔ A/D conversion system for AM/FM radio receivers , 2000 .

[19]  Gabor C. Temes,et al.  Switched-capacitor resonator structure with improved performance , 2001 .

[20]  Richard Schreier,et al.  Mismatch-shaping DAC for lowpass and bandpass multi-bit Delta-Sigma modulators , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[21]  R. J. van de Plassche,et al.  A sixth-order continuous-time bandpass sigma-delta modulator for digital radio IF , 1999, IEEE J. Solid State Circuits.

[22]  Saska Lindfors,et al.  On the design of 2nd order multi-bit /spl Delta//spl Sigma/-modulators , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[23]  Maurits Ortmanns,et al.  Implementation of a 1.5V low-power clock-jitter insensitive continuous-time /spl Sigma//spl Delta/ modulator , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[24]  A. Sedra,et al.  Quadrature bandpass ΔΣ modulation for digital radio , 1997, IEEE J. Solid State Circuits.

[25]  F. Henkel,et al.  A 1 MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[26]  Robert Henderson,et al.  A 19-bit low-power multibit sigma-delta ADC based on data weighted averaging , 1997 .

[27]  R. Castello,et al.  1.5 V High Performance S.C. Filters in BiCMOS Technology , 1990, ESSCIRC '90: Sixteenth European Solid-State Circuits Conference.

[28]  Gabor C. Temes,et al.  Direct-Charge-Transfer Pseudo-N-Path SC Circuit Insensitive to the Element Mismatch and Opamp Nonidealities , 2002 .

[29]  Ian Galton,et al.  A dynamic element matching technique for reduced-distortion multibit quantization in delta-sigma ADCs , 2001 .

[30]  Johan H. Huijsing,et al.  A 1.8-mW CMOS ΣΔ Modulator with Integrated Mixter for A/D Conversion of IF signals , 1999 .

[31]  A. Hairapetian,et al.  An 81 MHz IF receiver in CMOS , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[32]  K. Halonen,et al.  A dual-band RF front-end for WCDMA and GSM applications , 2001 .

[33]  J. F. Dickson,et al.  On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique , 1976 .

[34]  R.J. Van de Plassche,et al.  A monolithic 14-bit D/A converter , 1979, IEEE Journal of Solid-State Circuits.

[35]  L. Longo.  A 15b 30kHz bandpass sigma-delta modulator , 1993 .

[36]  Gabor C. Temes,et al.  A high-resolution multibit Sigma Delta ADC with digital correction and relaxed amplifier requirements , 1993 .

[37]  Shen-Iuan Liu,et al.  A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture , 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

[38]  R. T. Baird,et al.  A low oversampling ratio 14-b 500-kHz /spl Delta//spl Sigma/ ADC with a self-calibrated multibit DAC , 1996 .

[39]  T.C. Kuo,et al.  A very low power channel select filter for IS-95 CDMA receiver with on-chip tuning , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[40]  Ian Galton.  Spectral shaping of circuit errors in digital-to-analog converters , 1997 .

[41]  Michel Steyaert,et al.  Optimal parameters for single loop /spl Delta//spl Sigma/ modulators , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[42]  Vittorio Comino,et al.  A bandpass sigma-delta modulator IC with digital branch-mismatch correction , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[43]  Andrea Baschirotto,et al.  A 3.3-V CMOS 10.7-MHz sixth-order bandpass ΣΔ modulator with 74-dB dynamic range , 2001 .

[44]  Johan H. Huijsing,et al.  A 1.8-mW CMOS sigma delta modulator with integrated mixer for A/D conversion of IF signals , 2000 .

[45]  Michiel Steyaert,et al.  Low-IF topologies for high-performance analog front ends of fully integrated receivers , 1998 .

[46]  Jesper Steensgaard,et al.  Bootstrapped low-voltage analog switches , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[47]  Richard Schreier,et al.  Decimation for bandpass sigma-delta analog-to-digital conversion , 1990, IEEE International Symposium on Circuits and Systems.

[48]  Robert Henderson,et al.  Dynamic element matching techniques with arbitrary noise shaping function , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[49]  P. Kiss,et al.  Digital techniques for improved /spl Delta//spl Sigma/ data conversion , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

[50]  A. Abidi,et al.  A 3 . 3V 12b 50-MS / s A / D Converter in 0 . 6-m CMOS with over 80-dB SFDR , 2000 .

[51]  Bruce A. Wooley,et al.  A two-path bandpass ΣΔ modulator for digital IF extraction at 20 MHz , 1997 .

[52]  M. Waltari,et al.  A Self-Calibrated Pipeline ADC with 200 MHz IF-Sampling Frontend , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[53]  Gabor C. Temes,et al.  A 1-V 10-MHz clock-rate 13-bit CMOS /spl Delta//spl Sigma/ modulator using unity-gain-reset op amps , 2002 .

[54]  Gordon W. Roberts,et al.  An Eight-order Bandpass δ σl Modulator For A/D Conversion In Digital Radio , 1998 .

[55]  Michiel Steyaert,et al.  Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages , 1994, IEEE J. Solid State Circuits.

[56]  Howard C. Luong,et al.  A 70-MHz continuous-time CMOS band-pass /spl Sigma//spl Delta/ modulator for GSM receivers , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[57]  S. Jantzi,et al.  A fourth-order bandpass sigma-delta modulator , 1993 .

[58]  V.S.L. Cheung,et al.  A 1 V 10.7 MHz switched-opamp bandpass /spl Sigma//spl Delta/ modulator using doublesampling finite-gain-compensation technique , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[59]  K. Halonen,et al.  A dual-mode 80 MHz bandpass /spl Delta//spl Sigma/ modulator for a GSM/WCDMA IF-receiver , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[60]  T. Burger,et al.  A 13.5mW, 185 MSample/s /spl Delta//spl Sigma/-modulator for UMTS/GSM dual-standard IF reception , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[61]  Bruce A. Wooley,et al.  A 900-MHz RF front-end with integrated discrete-time filtering , 1996, IEEE J. Solid State Circuits.

[62]  A. Quesada,et al.  Programmable sine wave generator employing a mismatch-shaping DAC , 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

[63]  Hannu Tenhunen,et al.  Design of stable high order 1-bit sigma-delta modulators , 1990, IEEE International Symposium on Circuits and Systems.

[64]  W. M. Snelgrove,et al.  A 160-MHz fourth-order double-sampled SC bandpass sigma-delta modulator , 1998 .

[65]  Terri S. Fiez,et al.  Stability analysis of high-order delta-sigma modulation for ADC's , 1994 .

[66]  Kari Halonen,et al.  Bootstrapped switch without bulk effect in standard CMOS technology , 2002 .

[67]  Akira Yasuda,et al.  A fourth-order bandpass /spl Delta/-/spl Sigma/ modulator using second-order bandpass noise-shaping dynamic element matching , 2002 .

[68]  Saska Lindfors,et al.  A Dual-Mode 80MHz Bandpass DS-Modulator for a GSW/WCDMA IF-receiver , 2002 .

[69]  D. B. Ribner,et al.  Multistage bandpass delta sigma modulators , 1994 .

[70]  Eduard F. Stikvoort.  Some remarks on the stability and performance of the noise shaper or sigma-delta modulator , 1988, IEEE Trans. Commun..

[71]  A. Sedra,et al.  Quadrature bandpass /spl Delta//spl Sigma/ modulation for digital radio , 1997 .

[72]  Feng Chen,et al.  A High Resolution Multibit Sigma-Delta Modulator with Individual Level Averaging(Special Issue on the 1994 VLSI Circuits Symposium) , 1995 .

[73]  Gabor C. Temes,et al.  A 1-V, 10-MHz clock-rate, 13-bit CMOS ΔΣ modulator using unity-gain-reset opamps , 2001 .

[74]  Gerhard Tröster,et al.  An Interpolative Bandpass Converter on a 1.2μm BiCMOS Analog/Digital Array (Special Section on the 1992 VLSI Circuits Symposium) , 1993 .

[75]  Etsi Tc-Smg,et al.  European digital cellular telecommunications system (Phase 2); Radio transmission and reception (GSM 05.05) , 1994 .

[76]  A.A. Abidi,et al.  A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with over 80-dB SFDR , 2000, IEEE Journal of Solid-State Circuits.

[77]  A. Namdar,et al.  A 400-MHz, 12-bit, 18-mW, IF digitizer with mixer inside a sigma-delta modulator loop , 1999 .

[78]  Franco Maloberti,et al.  A 10.7-MHz N-Path Fourth-Order Bandpass Sigma-Delta Modulator , 1996, ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference.

[79]  William Martin Snelgrove,et al.  A 950-MHz IF second-order integrated LC bandpass delta-sigma modulator , 1998 .

[80]  William Martin Snelgrove,et al.  Switched-capacitor bandpass delta-sigma A/D modulation at 10.7 MHz , 1995, IEEE J. Solid State Circuits.

[81]  Saska Lindfors,et al.  N-path dynamic element matching for multibit bandpass ΣΔ modulators , 1997 .

[82]  Bang-Sup Song,et al.  A fourth-order bandpass delta-sigma modulator with reduced numbers of op amps , 1995 .

[83]  B. Leung,et al.  Multibit Sigma - Delta A/D converter incorporating a novel class of dynamic element matching techniques , 1992 .

[84]  R. Baird,et al.  Linearity enhancement of multibit /spl Delta//spl Sigma/ A/D and D/A converters using data weighted averaging , 1995 .

[85]  H. Tao,et al.  Analysis of timing jitter in bandpass sigma-delta modulators , 1999 .

[86]  R. Schreier,et al.  Noise-shaped multbit D/A convertor employing unit elements , 1995 .

[87]  G. Knoblinger,et al.  A new model for thermal channel noise of deep submicron MOSFETs and its application in RF-CMOS design , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[88]  Andrea Baschirotto,et al.  A 10.7MHz self–calibrated SC multibit 2nd–order bandpass Σ–Δ modulator , 2002 .

[89]  Eiji Takeda,et al.  An experimental 1.5-V 64-Mb DRAM , 1991 .

[90]  I. Galton,et al.  An audio ADC Delta-Sigma modulator with 100-dB peak SINAD and 102-dB DR using a second-order mismatch-shaping DAC , 2001, IEEE J. Solid State Circuits.

[91]  A. Wedel,et al.  An interpolative bandpass converter on a 1.2- mu m BiCMOS analog/digital array , 1993 .

[92]  N. Spencer.  An overview of digital telephony standards , 1998 .

[93]  B.A. Wooley,et al.  A wideband bandpass sigma-delta modulator for wireless applications , 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

[94]  Ian Galton,et al.  A Low-Complexity Dynamic Element Matching DAC for Direct Digital Synthesis , 1998 .

[95]  F. Chen,et al.  A 0.25-mW low-pass passive sigma-delta modulator with built-in mixer for a 10-MHz IF input , 1997 .

[96]  Gabor C. Temes,et al.  Oversampling Delta Sigma Data Converters , 1991 .

[97]  L. R. Carley,et al.  A noise-shaping coder topology for 15+ bit converters , 1989 .

[98]  Bernhard E. Boser,et al.  The Design of Sigma-Delta Modulation Analog-to-Digit a 1 Converters , 2004 .

[99]  Hannu Tenhunen,et al.  Phase noise in sampling and its importance to wideband multicarrier base station receivers , 1999, 1999 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings. ICASSP99 (Cat. No.99CH36258).

[100]  Howard C. Luong,et al.  A 70-MHz Continuous-Time CMOS Band-Pass ΣΔ Modulator for GSM Receivers , 2003 .

[101]  Saska Lindfors.  Behavior of a 1-bit 2nd-order /spl Delta//spl Sigma/-modulator under wideband excitation , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[102]  Gordon W. Roberts,et al.  An Eight-order Bandpass /spl delta/ /spl sigma/l Modulator For A/D Conversion In Digital Radio , 1998 .

[103]  Bruce A. Wooley,et al.  Second-order sigma-delta modulation for digital-audio signal acquisition , 1991 .

[104]  Akira Yasuda,et al.  A third-order ΔΣ modulator using second-order noise-shaping dynamic element matching , 1998, IEEE J. Solid State Circuits.

[105]  Saska Lindfors,et al.  A 80MHz band-pass ΔΣ-modulator for a 100MHz IF-receiver , 2001 .

[106]  J.F. Jensen,et al.  A bandpass /spl Sigma//spl Delta/ modulator with 92 dB SNR and center frequency continuously programmable from 0 to 70 MHz , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[107]  M. Rebeschini,et al.  A 16-b 160-kHz CMOS A/D converter using sigma-delta modulation , 1990 .

[108]  P. R. Gray,et al.  A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter , 1999, IEEE J. Solid State Circuits.

[109]  E.K.F. Lee,et al.  A 1.2V direct background digital tuned continuous-time bandpass sigma-delta modulator , 2001, Proceedings of the 27th European Solid-State Circuits Conference.

[110]  Shen-Iuan Liu,et al.  A double-sampling pseudo-two-path bandpass /spl Delta//spl Sigma/ modulator , 2000, IEEE Journal of Solid-State Circuits.

[111]  Shyh-Jye Jou,et al.  Low-power multirate architecture for IF digital frequency down converter , 1998 .

[112]  Andreas Kaiser,et al.  Input switch configuration suitable for rail-to-rail operation of switched-opamp circuits , 1999 .

[113]  G. Temes.  Delta-sigma data converters , 1994 .

[114]  Paul R. Gray,et al.  A 10 b, 20 Msample/s, 35 mW pipeline A/D converter , 1995, IEEE J. Solid State Circuits.

[115]  T. Salo,et al.  An 80MHz 8th-Order Bandpass DS-Modulator with a 75DB SNDR for IS-95 , 2002 .

[116]  Andrea Baschirotto,et al.  A 1V CMOS fully-differential switched-opamp bandpass Σ Δ modulator , 1997 .

[117]  T. C. Leslie,et al.  An improved sigma-delta modulator architecture , 1990, IEEE International Symposium on Circuits and Systems.

[118]  John W. Fattaruso,et al.  Self-calibration techniques for a second-order multibit sigma-delta modulator , 1993 .

[119]  B.A. Wooley,et al.  A two-path bandpass sigma-delta modulator with extended noise shaping , 2000, IEEE Journal of Solid-State Circuits.

[120]  J. M. Khoury,et al.  A 400-Ms/s frequency translating bandpass sigma-delta modulator , 1999, IEEE J. Solid State Circuits.

[121]  A.S. Sedra,et al.  Analog MOS integrated circuits for signal processing , 1987, Proceedings of the IEEE.

[122]  T. Varelas,et al.  A bipolar sampled-data bandpass delta-sigma A/D modulator , 1996, Proceedings of Custom Integrated Circuits Conference.

[123]  Howard C. Luong,et al.  A 1V 10.7MHz switched-opamp bandpass ∑Δ modulator using double- sampling finite-gain-compensation technique , 2001 .

[124]  Takafumi Yamaji,et al.  A fourth-order bandpass Δ-Σ modulator using second-order bandpass noise-shaping dynamic element matching , 2001 .