A Fully Integrated Point-of-Load Digital System Supply With PVT Compensation

This paper presents a fully integrated process, supply voltage, and temperature compensated supply (PVTCS) for a point-of-load digital system. Through adding the appropriate weighted threshold voltage variation from the pMOS (ΔVTHP) and the nMOS (ΔVTHN) diodes to the reference voltage of a high-speed low-dropout voltage regulator, the supply of the digital circuit becomes adaptive, and hence, it minimizes the speed deviation in the context of PVT variations. Validated in a UMC 65-nm CMOS process, the simulation and the measurement results of an inverter chain-based oscillator have validated the effectiveness of PVTCS. It can significantly reduce the delay variations with respect to the uncompensated supply counterpart. The same goes for a sample critical path-based oscillator with extensive simulation results. Therefore, the proposed circuit is useful for the digital point-of-load application, with the key technical merit of PVT compensation without encountering the potential latch-up problem from the reported methods.

[1]  Alessandro Trifiletti,et al.  A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Vivek De,et al.  Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[3]  Y. Ikeda,et al.  Mixed body bias techniques with fixed V/sub t/ and I/sub ds/ generation circuits , 2004, IEEE Journal of Solid-State Circuits.

[4]  Sachin S. Sapatnekar,et al.  Body Bias Voltage Computations for Process and Temperature Compensation , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  G. Ono,et al.  A 1000-MIPS/W microprocessor using speed adaptive threshold-voltage CMOS with forward bias , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[6]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .

[7]  M. Elmasry,et al.  NBTI and Process Variations Compensation Circuits Using Adaptive Body Bias , 2012, IEEE Transactions on Semiconductor Manufacturing.

[8]  K. Sakui,et al.  A CMOS bandgap reference circuit with sub-1-V operation , 1999 .

[9]  Y. Amemiya,et al.  A 300 nW, 15 ppm/$^{\circ}$C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs , 2009, IEEE Journal of Solid-State Circuits.

[10]  Y. Ikeda,et al.  Mixed body-bias techniques with fixed Vt and Ids generation circuits , 2005, 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005..

[11]  Kaushik Roy,et al.  On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Masayuki Miyazaki,et al.  An LSI system with locked in temperature insensitive state achieved by using body bias technique , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[13]  Vivek De,et al.  Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors , 2002, VLSIC 2002.

[14]  Eby G. Friedman,et al.  Active Filter-Based Hybrid On-Chip DC–DC Converter for Point-of-Load Voltage Regulation , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  W. Guggenbuhl,et al.  A versatile building block: the CMOS differential difference amplifier , 1987 .

[16]  Tetsuya Asai,et al.  An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs , 2010, IEICE Trans. Electron..

[17]  Xiao Liang Tan,et al.  A LDO Regulator With Weighted Current Feedback Technique for 0.47 nF–10 nF Capacitive Load , 2014, IEEE Journal of Solid-State Circuits.

[18]  Mohamed I. Elmasry,et al.  A Novel Low Area Overhead Direct Adaptive Body Bias (D-ABB) Circuit for Die-to-Die and Within-Die Variations Compensation , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[19]  Hidetoshi Onodera,et al.  An area effective forward/reverse body bias generator for within-die variability compensation , 2011, IEEE Asian Solid-State Circuits Conference 2011.

[20]  T. Chen,et al.  Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[21]  Mohamed I. Elmasry,et al.  On-Chip Process Variations Compensation Using an Analog Adaptive Body Bias (A-ABB) , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.