Automatic Structural Test Generation for Asynchronous Circuits

In this work we present a test method for asynchronous circuits, based on synchronous full scan techniques. By forcing the circuit to behave synchronously in test mode, it is possible to use high-quality standard test tools and equipment. It also implies standardization and interoperability with other tools and circuits. The work resulted in an operational automatic test system for asynchronous circuits. It has been verified on several examples, including an 80c51 micro-controller, an ADPCM speech codec and a Reed-Solomon error decoder. The quality of the resulting tests was high, with a stuck-at fault coverage of over 99%. However, making the circuit behave synchronously does impose a high penalty on the area. For the current implementation with a mainstream standardcell library the area overhead is around 90%. Implementations that use custom asynchronous cells reduce this to

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