A Scalable and Fast Microprocessor Design Space Exploration Methodology
暂无分享,去创建一个
Yuxing Tang | Lei Wang | Yu Deng | Feipeng Zhang | Qiang Dou | Guangda Zhang | Fangyan Qin | L. Wang | Q. Dou | Yuxing Tang | Guangda Zhang | Fei-Fan Zhang | Fangyan Qin | Yu Deng
[1] Krste Asanovic,et al. Accelerating Multiprocessor Simulation with a Memory Timestamp Record , 2005, IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005..
[2] Antonia Zhai,et al. Proceeding of the 41st annual international symposium on Computer architecuture , 2014, ISCA 2014.
[3] Somayeh Sardashti,et al. The gem5 simulator , 2011, CARN.
[4] K. G. Lockyer. An introduction to critical path analysis , 1965 .
[5] Fred W. Glover,et al. Future paths for integer programming and links to artificial intelligence , 1986, Comput. Oper. Res..
[6] Todd M. Austin,et al. The SimpleScalar tool set, version 2.0 , 1997, CARN.
[7] P. Bahr,et al. Sampling: Theory and Applications , 2020, Applied and Numerical Harmonic Analysis.
[8] Tianshi Chen,et al. ArchRanker: A ranking approach to design space exploration , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).
[9] Dam Sunwoo,et al. FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators , 2007, MICRO.
[10] Henk Corporaal,et al. Design space exploration algorithm for heterogeneous multi-processor embedded system design , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[11] Ed F. Deprettere,et al. A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).
[12] Lieven Eeckhout,et al. Memory Data Flow Modeling in Statistical Simulation for the Efficient Exploration of Microprocessor Design Spaces , 2008, IEEE Transactions on Computers.
[13] Jung Ho Ahn,et al. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[14] Kathryn A. Dowsland,et al. Simulated Annealing , 1989, Encyclopedia of GIS.
[15] F. Spitzer. Principles Of Random Walk , 1966 .
[16] Rahul Nagpal,et al. Criticality Driven Energy Aware Speculation for Speculative Multithreaded Processors , 2005, HiPC.
[17] Lei Wang,et al. HMCPA: Heuristic Method Utilizing Critical Path Analysis for Design Space Exploration of Superscalar Microprocessors , 2014 .
[18] James E. Smith,et al. Modeling superscalar processors via statistical simulation , 2001, Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques.
[19] R. Plackett,et al. THE DESIGN OF OPTIMUM MULTIFACTORIAL EXPERIMENTS , 1946 .
[20] Rastislav Bodík,et al. Focusing processor policies via critical-path prediction , 2001, Proceedings 28th Annual International Symposium on Computer Architecture.
[21] Emile H. L. Aarts,et al. Performance of the simulated annealing algorithm , 1987 .
[22] Ranga Vemuri,et al. Hardware software partitioning with integrated hardware design space exploration , 1998, Proceedings Design, Automation and Test in Europe.
[23] Milo M. K. Martin,et al. Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset , 2005, CARN.
[24] Emile H. L. Aarts,et al. Simulated Annealing: Theory and Applications , 1987, Mathematics and Its Applications.
[25] David M. Brooks,et al. Accurate and efficient regression modeling for microarchitectural performance and power prediction , 2006, ASPLOS XII.
[26] Richard Bellman,et al. ON A ROUTING PROBLEM , 1958 .
[27] Vijay Janapa Reddi,et al. WebCore: Architectural support for mobile Web browsing , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).
[28] Lieven Eeckhout,et al. Efficient Sampling Startup for Sampled Processor Simulation , 2005, HiPEAC.
[29] Stijn Eyerman,et al. Efficient Design Space Exploration of High Performance Embedded Out-of-Order Processors , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[30] Benjamin C. Lee,et al. Statistically Rigorous Regression Modeling for the Microprocessor Design Space , 2006 .
[31] Jaewon Lee,et al. RpStacks: Fast and Accurate Processor Design Space Exploration Using Representative Stall-Event Stacks , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.
[32] Damien Pous,et al. Hacking nondeterminism with induction and coinduction , 2015, Commun. ACM.
[33] Sally A. McKee,et al. Efficiently exploring architectural design spaces via predictive modeling , 2006, ASPLOS XII.
[34] Brad Calder,et al. Using SimPoint for accurate and efficient simulation , 2003, SIGMETRICS '03.
[35] Lieven Eeckhout,et al. Chip Multiprocessor Design Space Exploration through Statistical Simulation , 2009, IEEE Transactions on Computers.