Comparison of high-performance VLSI adders in the energy-delay space

In this paper, we motivate the concept of comparing very large scale integration adders based on their energy-delay characteristics and present results of our estimation technique. This stems from a need to make appropriate selection at the beginning of the design process. The estimation is quick, not requiring extensive simulation or use of computer-aided design tools, yet sufficiently accurate to provide guidance through various choices in the design process. We demonstrate the accuracy of the method by applying it to examples of high-performance 32- and 64-b adders in 100- and 130-nm CMOS technologies.

[1]  Cheng-Kok Koh,et al.  UST/DME: a clock tree router for general skew constraints , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[2]  Jens Vygen,et al.  Clock Scheduling and Clocktree Construction for High Performance ASICS , 2003, ICCAD 2003.

[3]  Ivan E. Sutherland,et al.  Logical effort: designing for speed on the back of an envelope , 1991 .

[4]  R. Tsay.  Exact zero skew , 1991, ICCAD 1991.

[5]  Masato Edahiro,et al.  A Clustering-Based Optimization Algorithm in Zero-Skew Routings , 1993, 30th ACM/IEEE Design Automation Conference.

[6]  Chandramouli V. Kashyap,et al.  Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Cheng-Kok Koh,et al.  Power supply noise suppression via clock skew scheduling , 2002, Proceedings International Symposium on Quality Electronic Design.

[8]  Simon Knowles,et al.  A family of adders , 1999, Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336).

[9]  Steven P. Levitan,et al.  VLSI DESIGN OF HIGH-SPEED, LOW-AREA ADDITION CIRCUITRY. , 1987 .

[10]  Atsushi Takahashi,et al.  Clock-tree routing realizing a clock-schedule for semi-synchronous circuits , 1997, ICCAD 1997.

[11]  Vojin G. Oklobdzija,et al.  High-performance system design : circuits and logic , 1999 .

[12]  Vojin G. Oklobdzija,et al.  Multiplexer based adder for media signal processing , 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

[13]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[14]  R. Krishnamurthy,et al.  A 4 GHz 130 nm address generation unit with 32-bit sparse-tree adder core , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[15]  K. Soumyanath,et al.  Sub-500 ps 64 b ALUs in 0.18 /spl mu/m SOI/bulk CMOS: Design & scaling trends , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[16]  Jan-Ming Ho,et al.  Zero skew clock routing with minimum wirelength , 1992 .

[17]  Sanu Mathew,et al.  Energy-delay estimation technique for high-performance microprocessor VLSI adders , 2003, Proceedings 2003 16th IEEE Symposium on Computer Arithmetic.

[18]  Eby G. Friedman,et al.  Clock skew scheduling for improved reliability via quadratic programming , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[19]  Jason Cong,et al.  Bounded-skew clock and Steiner routing , 1998, TODE.

[20]  Vojin G. Oklobdzija,et al.  On Implementing Addition in VLSI Technology , 1988, J. Parallel Distributed Comput..

[21]  Chung-Kuan Cheng,et al.  Skew Sensitivity Minimization Of Buffered Clock Tree , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[22]  Harold S. Stone,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.

[23]  K. Soumyanath,et al.  Sub-500-ps 64-b ALUs in 0 . 18-m SOI / Bulk CMOS : Design and Scaling Trends , 2001 .

[24]  S.H. Dhong,et al.  470 ps 64-bit parallel binary adder [for CPU chip] , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[25]  S. Naffziger,et al.  Statistical clock skew modeling with data delay variations , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[26]  S. Naffziger.  A sub-nanosecond 0.5 /spl mu/m 64 b adder design , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[27]  Hoang Dao,et al.  Application of logical effort techniques for speed optimization and analysis of representative adders , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).

[28]  V.G. Oklobdzija,et al.  Application of logical effort on delay analysis of 64-bit static carry-lookahead adder , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).

[29]  Robert H. Dennard,et al.  CMOS scaling for high performance and low power-the next ten years , 1995, Proc. IEEE.