Performance predictions of scaled BiCMOS gates using physical simulation

The necessary reduction in supply voltage for future scaled-down BiCMOS technologies will cause a degradation in speed because the base-emitter forward voltage drop is not scaled. The analysis of how the performance difference between BiCMOS and CMOS changes with scaling has been ambiguous in previous work because of insufficient model accuracy. In this work, mixed-level device-circuit simulation with accurate numerical device models, used to predict gate delay, output voltage drop, breakdown voltage and hot-carrier reliability estimates for BiCMOS and CMOS structures with different scaling, is described. A very significant result was that for 0.25- mu m feature size the bipolar part of BiCMOS will still contribute to performance if the fan-out is high and if appropriate scaling including doping, supply voltage, vertical dimensions, and lateral dimensions is used. >

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