One kind of a pseudo-parallel multiplier coder for variable coefficients csd

The present invention relates to integrated circuit technology, and more particularly relates to a parallel encoder pseudo CSD multiplier coefficients for a variant. CSD pseudo parallel encoder of the present invention, the logic circuit includes an arithmetic logic circuit and an output; input end of the external input data arithmetic logic circuit, the logic circuit outputs a first termination operation input; the output of the logic circuit a second input terminal of the external input data, after which the coefficient multiplier output stage input terminated. Advantageous effects of the present invention is the code system in the guarantee pseudo CSD encoded with the conventional CSD encoding the same non-zero number of bits simultaneously, using parallel arithmetic logic eliminating carry propagation logic conventional CSD encoding process is generated, thereby improving the dummy CSD computing speed encoder, encoding it with a desired length independent of binary digits, belongs to a fixed delay encoding circuit, which greatly improves data throughput pseudo CSD encoder. In particular, the present invention is applicable to a parallel dummy variable coefficient multiplier CSD encoder.