论文信息 - Submicron super TFTs for 3-D VLSI applications

Submicron super TFTs for 3-D VLSI applications

High performance submicron super TFTs are reported. A novel grain enhancement method is used to form large single grain silicon at the channel region of the TFT, making its structure comparable to SOI MOSFET. The process can be performed with high controllability, thus giving much smaller device-to-device variation compared to conventional TFT process. The reported n-channel super TFT displays a subthreshold swing of 72 mV/dec, g/sub max/=198 mS/mm and an I/sub dast/ of 0.3 mA//spl mu/m at V/sub g/-V/sub t/=1.5 V, with L/sub G/=0.4 /spl mu/m and t/sub ox/=110 /spl Aring/. The super TFT technology will facilitate the formation of three-dimensional (3-D) VLSI circuits and double gate CMOS.

[1] M. Chan,et al. Single grain thin-film-transistor (TFT) with SOI CMOS performance formed by metal-induced-lateral-crystallization , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[2] V. Subramanian,et al. Low-leakage germanium-seeded laterally-crystallized single-grain 100-nm TFTs for vertical integration applications , 1999, IEEE Electron Device Letters.

[3] P. Ko,et al. SOI formation from amorphous silicon by metal-induced-lateral-crystallization (MILC) and subsequent high temperature annealing , 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

[4] S. Maeda,et al. High Performance Gate-all-around TFT(GAT) For High-density, Low-voltage-operation, And Low-power Srams , 1997, Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications.

[6] Krishna C. Saraswat,et al. High-performance germanium-seeded laterally crystallized TFTs for vertical device integration , 1998 .

[7] Seung-Ki Joo,et al. Low temperature poly-Si thin-film transistor fabrication by metal-induced lateral crystallization , 1996 .

[8] Seung-Ki Joo,et al. PD INDUCED LATERAL CRYSTALLIZATION OF AMORPHOUS SI THIN FILMS , 1995 .

[9] Shigenobu Maeda,et al. An asymmetric memory cell using a C-TFT for single-bit-line SRAM's , 1999 .